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lei1
Visitor
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Registered: ‎03-19-2015

AXI-4 addressing (read command)

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Hello everone,

 

I created a DDR3-Interface using the MIG-IP connected via AXI with an interconnect. I designed an own control-master-module. Therefor I used the "create and package IP" tool and modiefied the axi-code for my own purpose. So far, so good.

Writing is working properly.

When I try to readout the written bytes, the axi-araddress is set to a value and handed over to the mig-module. The correct address can be monitored through the different modules. At the end the correct address reaches the mig-module.

But, the read-data, that returns is not what I would expect.

It seems as if the last two bits of the read-address (araddr) are not interpreted at all. Example: If I set the address to "0000 1011" the readout begins with byte no. 2.
I checked all connections, they are correct. Is there something I don't see?

 

Thanks in advance!
Lei

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vsrunga
Xilinx Employee
Xilinx Employee
11,448 Views
Registered: ‎07-11-2011

@lei1,

 

I think your observation is correct.

Please look into AXI Addressing mapping section of UG586 for more details 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_4/ug586_7Series_MIS.pdf 

Based on UI, Memory data width and nck_per_clock ratio AXI Byte address lower bits will get masked.

Black boxes shoes possible cases of 2 bit masking.

 

 

 

AXI_addressing.png

 

 

Hope this helps,

Vanitha 

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muzaffer
Teacher
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Registered: ‎03-31-2012
How do you know if writing is working properly? Maybe you are not writing the correct data at the right address. What do you set for strobes when you write?
Also what data do you write to what address and what do you read. Start with some simple aligned writes/reads and see if you can figure where the issue is.
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vsrunga
Xilinx Employee
Xilinx Employee
11,449 Views
Registered: ‎07-11-2011

@lei1,

 

I think your observation is correct.

Please look into AXI Addressing mapping section of UG586 for more details 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_4/ug586_7Series_MIS.pdf 

Based on UI, Memory data width and nck_per_clock ratio AXI Byte address lower bits will get masked.

Black boxes shoes possible cases of 2 bit masking.

 

 

 

AXI_addressing.png

 

 

Hope this helps,

Vanitha 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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lei1
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Registered: ‎03-19-2015

Thank you all for your replies.

Indeed, this is exactly what I was searching for.

 

Great, this shows my testing is not completely nonsense :)

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jmjohns8
Visitor
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614 Views
Registered: ‎11-21-2019

Similar problem in another thread. Bumping this one with hopes one of the previous responders can offer some insight.

https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/64-bit-SDRAM-access-from-PL-on-ZCU-102-board-reads-wrong-value/m-p/1067300 

Thanks in advance!

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