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Observer
Observer
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Registered: ‎08-13-2014

AXI Interface - after a while wready is static high but interface is not ready

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Hi,

in my current design i have implemented an AXI Smartconnect IP 1.0 connected with DDR3 MIG 1.4. I started with Vivado 2016.4 to build this system (with AXI  Interconnect) and because of the "ready" issue I also upgraded whole design to latest VIvado 2019.1. The issue keeps on annoying me.

In the following picture you can see a part of my design...IP_integrator.JPG

There are 3 AXI Ports which are abitrated by a Smartconnect 1.0. All Ports are in same clockdomain (200 MHz) but S00_AXI (250 MHz). So between S00_AXI and M00_AXI is a clock domain crossing.Data width is 256 Bit on S00_AXI and others ports/internal smartconnect data width is bits. Normal usage should be to write data via S00_AXI into memory and read back data via S01_AXI.

 

The issue i can see is that after some time writing data via S00_AXI Port into DDR3 memory (8GB) it can happen that the wready signal on data port keeps on static high. But the interface seems not to be ready for receiveing data because reading back data shows me that there are missing some data words. 

When everything works fine without data corruption wready signal on S00_AXI goes low from time to time after i set a request on adress port. As soon as i have data corruption the wready signal is static high all the time. So my AXI master connected to S00_AXI writes data alle the time after request was done but the interface is not ready ... Btw master on AXI_S00 is 3rd party DMA IP Core.

Follwoing pictures shows the differences...

Without data corruption

write_ok.JPG

 

 

and than with data corruption and static wready signal

write_fail.JPG

Up to now i only see this issue in hardware. I was not able to reproduce this behavior in simulation.

 

Can anyone help?

 

Thanks in advance...

 

Regards Torsten

 

 

 

 

 

 

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Observer
Observer
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Registered: ‎08-13-2014

Re: AXI Interface - after a while wready is static high but interface is not ready

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@florentw wrote:

This can be another reason haha.

 


Really? Is that the way Xilinx tries to support it's customers? 

I already spent, oh sorry, waste is the right word ... waste so much time with bugs caused by the creepy toolchain ... there are so many threads in this forum without any answers or solutions. We, the customers, buy the FPGAs, we buy the licences for your tools and than there is no one which is able to do serious support.

Normally i would find answers like "haha" in a troll forum...sry that is not that expertise i expect.

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: AXI Interface - after a while wready is static high but interface is not ready

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Hi @tdittrich 

If you can reproduce the issue only in HW I could check arround timing:

  • Is your design meeting timing?
  • Do you have the correct constraints?

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer
Observer
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Registered: ‎08-13-2014

Re: AXI Interface - after a while wready is static high but interface is not ready

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Hi @florentw 

thanks for repsonse, desing meets timing and constraints should be ok.

Up to now it looks like the master which is writing data into S00_AXI do not hold wvalid signal until wready is high in some situations. AXI Protocol checker rises corresponding error bit in status vector.

Best regards...

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: AXI Interface - after a while wready is static high but interface is not ready

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HI @tdittrich 

This can be another reason haha.

Good to konw that you are making progress.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Highlighted
Observer
Observer
488 Views
Registered: ‎08-13-2014

Re: AXI Interface - after a while wready is static high but interface is not ready

Jump to solution

@florentw wrote:

This can be another reason haha.

 


Really? Is that the way Xilinx tries to support it's customers? 

I already spent, oh sorry, waste is the right word ... waste so much time with bugs caused by the creepy toolchain ... there are so many threads in this forum without any answers or solutions. We, the customers, buy the FPGAs, we buy the licences for your tools and than there is no one which is able to do serious support.

Normally i would find answers like "haha" in a troll forum...sry that is not that expertise i expect.

 

 

View solution in original post

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: AXI Interface - after a while wready is static high but interface is not ready

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Hi @tdittrich 

Sorry to try to be friendly... the forums is a community, this is how I would be in real life.

Sorry you just want somebody serious (ps, we can do serious support without just writing formal replies).

I tried to help you but I cannot always think about all the options. You add a good lead and you shared it. I gave you a kudos. And if you required more help I would have assisted you.

You have a FAE which should be your primary point of contact for support or to give feedback if you are not ahppy with the tool. Xilinx forums give you a bit more.

Yes, there are still threads in this forum without any answers or solutions, but it improved in the last few years and it is way less common. I am moderator on the video board and the solution rate is ~80% (but the nearly all topic are solved, only members are not replying when they have a reply).

Solving issue and participating in the community is what motivates me. You will not get formal replies with me but I will be here to help.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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