AXI interface for LPDDR MIG

[hmleland.mms.rf]

What is the reason that the LPDDR MIG does not support an AXI interface and thus cannot be used in IPI design flow?  Is there a workaround?

Using Vivado 2019.2 and UltraScale+ family parts.

Thanks!

H

[kren]

LPDDR is only supported on Zynq Ultrascale+ within its PS. Please check with this.

[rpr]

Hi @hmleland.mms.rf 

MIG LPDDR IP doesn't support with AXI interface, following link provides packaging IP & IPI.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1118-vivado-creating-packaging-custom-ip.pdf

[hmleland.mms.rf]

The DDR MIG supports an AXI interface and has the same memory interface as LPDDR (app_en, app_hi_pri, app_addr, app_cmd, etc.).  The work has already been done by Xilinx to support AXI for DDR so why is that excluded from LPDDR.  What is the reason that Xilinx does not support the AXI for LPDDR but does for DDR?  Are there technical limitations with LPDDR that prevent it or did Xilinx choose not to provide it?