So I stumbled upon something today. The custom V6 board design I have has my DDR pins being on bank 34, EXCEPT for the ODT (on die termination) pin being on bank 14. No biggie except that bank 14 is being used for my ADCs and is setup for 2.5V and my DDR2 (MT47H256M8) is running at 1.8V. So bank 14 complains about having LVDS_25 on it when I need to be using SSTL18_II for the ODT.
Now, is there anyway to know if the MIG design is actually using the ODT? If it isn't, I am assuming that I can set it to LVDS_25 in the ucf and then just ground it in my design to 1'b0, but I am guessing I won't be that lucky.
One thing that is a littler interesting is this page from the datasheet for the flash (see attached), and its Vclamp. Is that the voltage ABOVE the 1.8V? If so, it seems like I might be able to use the LVDS_25 as a Vclamp of 0.7V doesn't seem horrible (again though, I imagine that it can't be that easy....).
MIG most likely is using ODT, if your design has the pin assigned. You miay be able to change MIG settings not to use ODT, but then you need to have proper board-level termination on the DQ lines.
Also on changing the IO standard. I'm pretty sure that ODT is a single-ended signal for DDR2. You could change the standard to LVCMOS25 or SSTL2, but LVDS would need a differential pair. It is possible that LVCMOS25 with sufficiently low output drive current setting, or SSTL2_I would not overdrive ODT the pin, but it's not an experiment I'd want to make. Do you intend to make a lot of these boards? It would be much better to move ODT to a 1.8V bank. Also, does your board have a series resistor on the ODT signal? That could help reduce the signal swing, or geve an easier way to wire a different FPGA IO pin to the signal.