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cvasselin
Observer
Observer
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Registered: ‎08-02-2018

Axi Stream FIFO interface

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Hi,

I'm trying to find a way to transfer data coming from an ADC device (64 bit wide I+Q, frequency ~500Ksample max) to the PS side (ARM).

I found the Axi Stream IP core that could match with my need but not sure. I need a buffer of 4096 *64 bits.

Registers of this IP are reachable starting from C_BASEADDR as described in the Xilinx documentation.

I use Vivado 218.3 and I can get the Base address with the Address Editor; adresses starting from 0x43C0 0000 for S_AXI interface and 0x43C1 0000 for S_AXI_FULL interface.

My questions :

- Where is the adress space of the Fifo (or memory map adress) ? Is this adress space located after the register space ?

-  What the use of the AXI_FULL interface (I did dot see anything about this interface in the documentation) ?

Best regards,

 

 

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Axi-Stream-Fifo-Registers.JPG
Axi-Stream-Fifo-Adresses.JPG
Axi-Stream-Global-Vue.JPG
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vanmierlo
Mentor
Mentor
937 Views
Registered: ‎06-10-2008

Only the registers are memory mapped. The fifo contents are not directly addressable. You can push or pop values through the registers. There is little to no advantage from using the AXIFULL interface unless you program a generic DMA controller to transfer data. I suggest to disable it.

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vanmierlo
Mentor
Mentor
938 Views
Registered: ‎06-10-2008

Only the registers are memory mapped. The fifo contents are not directly addressable. You can push or pop values through the registers. There is little to no advantage from using the AXIFULL interface unless you program a generic DMA controller to transfer data. I suggest to disable it.

View solution in original post