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352 Views
Registered: ‎10-24-2019

Built-In Self-Test (BIST)

Hello everyone,

I am trying to test my PL DDR in ZCU104 Board. I installed the DDR4 SODIMM in PL side and I have tested my board with Built-In Self-Test (BIST). I got an failure in my test. What is this due to? There is a datasheet about SODIMM ,which I used in below. Can you help me to solve this problem.

Thank you

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7 Replies
Teacher drjohnsmith
Teacher
342 Views
Registered: ‎07-09-2009

Re: Built-In Self-Test (BIST)

If you look at your test 2 it says you have data bits stuck together,
this is also reflected in test 4.

Has this board run with other SODIMM ?
suggest you try another stick of memory from another manufacturer,
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Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎03-04-2018

Re: Built-In Self-Test (BIST)

Hello aysenurakinci805@gmail.com 

 

I’m not fully understand your query, but will try to answer.

From the UG1267(ZCU104 Board User Guide), Micron SIDIMM is used on PL-Side as DDR4.  First of all, why do you use the KVR26S196?  Could you please try the Micron?

https://www.xilinx.com/support/documentation/boards_and_kits/zcu104/ug1267-zcu104-eval-bd.pdf

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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zcu104.PNG
254 Views
Registered: ‎10-24-2019

Re: Built-In Self-Test (BIST)

Thank you for interest. It might work with recommended SODIMM, I will try it but I wonder, can I work x16 SODIMM in ZCU104 board? 

Thank you

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Xilinx Employee
Xilinx Employee
214 Views
Registered: ‎03-04-2018

Re: Built-In Self-Test (BIST)

Hello aysenurakinci805@gmail.com ,

 

If you want to work other memory parts, please check the DDR configuration as custom parts.  Attached is an example.

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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ps_ddr.PNG
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179 Views
Registered: ‎10-24-2019

Re: Built-In Self-Test (BIST)

Are these configurations for the PL side DDR?

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Xilinx Employee
Xilinx Employee
174 Views
Registered: ‎03-04-2018

Re: Built-In Self-Test (BIST)

Hello aysenurakinci805@gmail.com ,

 

No, it is the PS DDR configuration.  Create Block design, then add the Zynq as shown the Figure.

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------

zynq.PNG
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163 Views
Registered: ‎10-24-2019

Re: Built-In Self-Test (BIST)

Hi kshimizu,

Thanks for interest, but I want to configure PL side. I have 2 question.
First question: I have selected x16 device in VCU DDR Controller IP but I get some errors. I am trying to solve this problem now. How can I solve this problem? Problem is seen in below.
Second question: When I use x8 device without ECC, do I need to configure anything in my design?

Screenshot from 2019-11-29 10-29-27.png
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