04-08-2021 02:13 AM
I want to implement the DDR MIG IP example design on hardware. I am trying to run MIG 3.61 code(RTL) (I have attached the MIG configuration in the attachments) generated from Xilinx MIG on the Virtex Xilinx ML505 evaluation platform, Work environment is ISE 13.2 & ISE 14.7. The MIG generated code implements and generates a bit file but fails to simulate giving the following initialization error.
ERROR: Activate Failure. Initialization sequence is not complete.
I have gone through ug086.pdf and as it is MIG-produced example_design I'm pretty sure I'm messing up somewhere. The code should work out of the box, right? Could you help me out with this one? If anyone could guide me in the right direction, that'd be awesome!
04-09-2021 02:45 AM
Please try to run behavirol simulation? Is it successful?