01-09-2015 02:54 AM
I am trying to interface DDR SDRAM using MIG.
I sucessfully got init_done (initilization done) signal i.e. DDR is properly caliberated and initiallized.
Since all Read/Write data, Read/Write enable signals and Addresses and synchronised with clock_tb,
so i tried to trace all these (Read/Write data and Addresses).
I am using clock_tb as chipscope clock but all traced buses (Read/Write data and Addresses) shows only constant values for whole of the tracing period. why?
Is MIG in/out signals (Read/Write data and Addresses) is traceable or not?
01-09-2015 03:21 AM
Which device are you using?
How are you driving the data and is this with the example design or your own design?
What is the trigger for the debug core?
There will be Debug signals for Memory controller option in the GUI while generating the core and if you enable it the debug
core will be connected by default in the core and can be used for debugging.
01-11-2015 04:54 AM - edited 01-11-2015 04:55 AM
I am using V4 Fx12.
This is my own "User Design" not Example Design.
MIG is set disabled for debug.
Trigger is for any time: X (not set for 1 or 0).
01-11-2015 03:59 PM
If you enable debug option while MIG generation you will be able to see all calibration related signals. But ILA cores will be properly generated only with example design.
Please go through UG586 hardware debug section for more details on list of signals.
For user design you can comment out the traffic gen and have your own FSM driving app_* signals.
If you wish to capture app_* signals then user your own ILA and have proper trigger conditions else you might not be able to see the correct signal transitions.
Hope this helps