08-26-2011 11:41 AM
After all, good afternoon.
We are working with a Trenz Electronic Board with a Spartan3E-1200k FPGA, but in the implementation we have a problem, the DDR never initialize.
We generate a MIG and Develop a module to control the MIG, we test the code with a TEST_BENCH and in a Digilent Spartan-3E Starter Kit Board that have the same DDR Device than the Trenz Electronic one ( MT46V32M16 ), and it works correctly.
We observed that in the Trenz Electronic Board, the signal named cntrl0_sys_rst180_tb that becomes from the MIG module, never go to falling edge.
It is supossed that the cntrl0_sys_rst180_tb signal becomes to a falling edge when the DDR stabilize their voltage.
What are the possible error that cause that issue?
NOTE: i attached the UCF file that we use, is the same that we use for the Digilent Spartan-3E Starter Kit Board, Iattached too the diagram of the hardware for that Board.
08-26-2011 12:59 PM
The Board Voltage are stable, why the DDR never stabilize their voltage? or there is another reazon for that issue?
08-28-2011 11:17 AM
I see you have problems with MIG core on Trenz Micromodule.
The module is verified with MIG core in conjunction with Microblaze soft processor. The Multiport Memory Controller uses MIG PHY. Unfortunatelly there is no MIG project from Trenz for the ones which prefer non-Microblaze designs.
About your problem: I would check the clock and reset of the MIG core. According to your post MIG core never comes out of the reset. The reset sequence does not wait for DDR to stabilize voltage, but initializes DCM and MIG logic.
All voltages stabilize immediatelly after power up, long before the FPGA is configured.
The questions are:
Is the DCM properly configured? Input clock is 100MHz.
Pins are slightly different from the ones generated by MIG tool. Did your design meet timing?
Did you check the reset polarity? This is a common problem at startup.
Does the LED turn ON? There is one signal connected to it (end of reset sequence?)
Did you try to use Chipscope to see what is going on inside the FPGA?
MIG Coregen project can include Chipscope core if selected.
I hope this helps.
PS: Trenz Electronic has a great forum. I will be glad to answer your questions.