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Visitor arevhamb
Visitor
876 Views
Registered: ‎10-10-2017

DDR2 Memory interface generation with MIG 7

Hello All,

 

I'm using Vivado 2017.2 MIG 7 series IP to generate memory interface for DDR2 SDRAM, on Kintex-7.

 

Does anybody knows if it is possible to generate memory interface for MT47H64M8SH-25E, providing correct parameters, and selecting MT47H64M16XX-25/25E?

 

Thank you in advance.

 

Arevik

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3 Replies
Moderator
Moderator
822 Views
Registered: ‎09-18-2014

Re: DDR2 Memory interface generation with MIG 7

Arevhamb,

 

Do you have 2017.2 installed? If so why not just test out Vivado and whip out the MIP IP select your basic settings then on the memory device page see if that part is selectable... If you don't, check out this article as well as this one for the actual list. Do note you can create custom parts if not shown there as well. View the Memory design assistant articles for more info. 

 

 

From the IP it looks like the base MT47H64M8SH-25 is supported. 

 

 MIG_EX.PNG

 

Regards,

T

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Newbie h1rih1r1n
Newbie
252 Views
Registered: ‎03-01-2019

Re: DDR2 Memory interface generation with MIG 7

I have created mig 7 series ip but how to interface ddr2 in that mig 7 series ip? ThankYou in advance.

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Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎08-21-2007

Re: DDR2 Memory interface generation with MIG 7

You can refer to document UG586 to learn the interface. You can also right-click the MIG IP (.xci file) to generate a IP example design.

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