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Newbie
Newbie
2,371 Views
Registered: ‎02-17-2016

DDR3 KC705 at 200 MHz with 64 bit bus

Hi ,

 

I tried the MIG interface for the following configuration (800 MHz , 64 bit bus ) , I am using vivado 2016.2. In the simulation I am able to read and write to the DDR3 memory. When the design is implemented and programed to the KC705 board I notice the followin g

1) Init complete is not going high

2) No app_rdy ==1 condition happens even when the app_en signal is set high .

 

Would appreciate any working reference model with ucf file.

 

With regards

 

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Explorer
Explorer
2,347 Views
Registered: ‎04-05-2016

Re: DDR3 KC705 at 200 MHz with 64 bit bus

It is a bit dated ( 2014 ), but there is a step-by-step guide to create a MIG design using Vivado targeting the KC705 board:

https://www.xilinx.com/support/documentation/boards_and_kits/kc705/2014_3/xtp196-kc705-mig-c-2014-3.pdf

Did you check the KC705 board to ensure the DDR SODIMM is seated correctly ( and present )?
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Moderator
Moderator
2,325 Views
Registered: ‎02-11-2014

Re: DDR3 KC705 at 200 MHz with 64 bit bus

Hey @vintu_dsi,

 

@timduffy is correct. This reference design even though was last verified in 2014.3 should still apply to 2016.2. You can find a sample XDC in the associated RDF found here: https://www.xilinx.com/member/forms/download/design-license.html?cid=379235&filename=rdf0281-kc705-base-trd-2014-3.zip. it is called example_top.xdc. We also have a bitsrtream ready for testing on the KC705 available in the same RDF and it is called example_top.bit.

 

Thanks,
Cory

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