08-10-2017 03:10 AM
I tried the MIG interface for the following configuration (800 MHz , 64 bit bus ) , I am using vivado 2016.2. In the simulation I am able to read and write to the DDR3 memory. When the design is implemented and programed to the KC705 board I notice the followin g
1) Init complete is not going high
2) No app_rdy ==1 condition happens even when the app_en signal is set high .
Would appreciate any working reference model with ucf file.
08-10-2017 05:15 AM
08-10-2017 08:28 AM
@timduffy is correct. This reference design even though was last verified in 2014.3 should still apply to 2016.2. You can find a sample XDC in the associated RDF found here: https://www.xilinx.com/member/forms/download/design-license.html?cid=379235&filename=rdf0281-kc705-base-trd-2014-3.zip. it is called example_top.xdc. We also have a bitsrtream ready for testing on the KC705 available in the same RDF and it is called example_top.bit.