02-28-2019 11:39 AM
I am trying to configure the DDR3 MIG in ping-pong mode.
So I go to the IP catalog, pick DDR3 SDRAM (MIG) (1.4), select Physical Layer PingPong and configure the clocking options, memory part number and so on. After cliking OK, I get the file ddr3_0.xci in ddr3_ping_pong/ddr3_ping_pong.srcs/sources_1/ip/ddr3_0.
Now I want to be able to use this IP in a block design. I follow the instructions in AR# 60700: Vivado IP Integrator - How can I add an Xilinx IP into my packaged IP to use in my Block Design.
I edit the template /ddr3_ping_pong.srcs/sources_1/ip/ddr3_0/ddr3_0.veo to create a wrapper ddr3_mig_ip.v which instantiates module ddr3_0.
So far so good. But this is where I am having problems.
I click on Tools --> Create and Package New IP --> Next --> Package your current project --> Next and I get the message "No modules were found in your design".
The AR# 60700 mentions to click on Out-of-Context Settings in Generate Output Products and deselect the ddr3_0.xci box.
But I don't see the Out-of-Context Settings option (I am using Vivado 2018.2) (I right-click on ddr3_0 in IP Sources and select Generate Output Products).
What am I doing wrong?
02-28-2019 12:20 PM
If I understand your question... you want to know how to enable out-of-context in Vivado...
In settings... under synthesis... in the options areas... in the 'More Options' box... type -mode out_of_context
Hope that helps
If so, please mark as solution accepted. Kudos also welecomed. :-)
02-28-2019 07:52 PM
I am getting this error:
[IP_Flow 19-5108] Filegroup 'xilinx_anylanguagesynthesis': XCI file 'ddr3_0.xci' cannot be packaged in the same directory as the component.xml. Please create subdirectories for subcore XCI files
Do I need to create a separate directory for the ddr3_0.xci file?
03-01-2019 01:33 PM
I solved this issue. I now have a DDR3 Memory Controller IP in Ping Pong Mode. Next step is to add an AXI interface.