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prasanthvthycaud
Adventurer
Adventurer
1,622 Views
Registered: ‎12-24-2013

DDR3 MIG User Interface Clock

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Hi All,

 

I wanted use a DDR3 MIG Controller (Kintex 7 FPGA) for my design, I am having a doubt on User Interface clock for a native interface controller, will i able to generate the user interface clock based on my requirement. I wanted to make the user interface clock to 125Mhz and controller clock to 800Mhz.

 

In IP Core Generator I could see that controller clock and user interface clock has to be in relation in such a way that it can be either 1/2 or 1/4.

 

Regards,

Prasanth

 

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vemulad
Xilinx Employee
Xilinx Employee
1,923 Views
Registered: ‎09-20-2012

Hi @prasanthvthycaud

 

Yes that's correct, the ui_clk frequency is 1/4th or 1/2 of ddr3_clk frequency based on PHY to controller ratio selected in IP. This clock relationship is fixed. 

 

 

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
1,924 Views
Registered: ‎09-20-2012

Hi @prasanthvthycaud

 

Yes that's correct, the ui_clk frequency is 1/4th or 1/2 of ddr3_clk frequency based on PHY to controller ratio selected in IP. This clock relationship is fixed. 

 

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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