02-05-2020 08:14 AM
I'm using a DDR3 with an ARTIX 7 and use a MIG to interface MicroBlaze with DDR3. In the MIG Configuration window, I have a problem with the Pin Selection page. In fact, the "Validate" operation terminates with this error message :
I think, I've followed all rules explain in the "Design Guidelines" of UG589 and all the address / control pins are on byte group pins (T2 and T3).
Could you please help to understand this error.
Here is my configuration :
In attachment, I also send the UCF file of my design for the DDR3
02-05-2020 10:09 AM
02-09-2020 11:49 PM
Please let me know the FPGA part and package. I'll check.
02-09-2020 11:57 PM
Thank you for your reply. I'm using an Artix7 XC7A35T-1CSG325C.
I've seen that when I put DDR3_CK on T3, the validatation succeed.But, this constraint was not present on UG586 and my board has already been designed. So my question is, if I put DDR3_CK on T3 in the MIG configuration and then put DDR3_CK on T2 (has designed on the PCB), is it OK ?
02-10-2020 11:25 PM
The ddr3_odt is placed on R6 which is not memory byte group pin (not in T0, T1, T2 or T3), but adjacent to T3. When T3 is for address/control signal and CK is included, it will pass the pinout rules, just as the error message told.
The pinout with IP wizard should match with the board layout. If not， the memory controller cannot work normally.
02-11-2020 12:10 AM
Hi Kren and thanks for this reply.
I don't need speed for the DDR3 and I understand the MIG will not work normally but will it still work ?
02-11-2020 12:17 AM
No, it can't work, because the calibration will get failed.
02-11-2020 01:26 AM
02-11-2020 02:09 AM
You can find this rule in "bank and pin selection guides for DDR3 designs" in ug586. You can find the lastest version at: https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf