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1,036 Views
Registered: ‎09-23-2019

DDR3 Pin Selection

Hi,

I'm using a DDR3 with an ARTIX 7 and use a MIG to interface MicroBlaze with DDR3. In the MIG Configuration window, I have a problem with the Pin Selection page. In fact, the "Validate" operation terminates with this error message :

  • ERROR : Address ports can be allocated to non memory byte group pins (not in T0, T1, T2 or T3) if and only if its adjacent byte is non Data byte group (i.e either Address/Control or empty) and it should contain at least one unallocated pin or allocated with memory clock pair. Refer to UG586 and AR# 45588 for more information.

I think, I've followed all rules explain in the "Design Guidelines" of UG589 and all the address / control pins are on byte group pins (T2 and T3).

Could you please help to understand this error.

Here is my configuration :

  • Vivado v2019.1.3
  • Windows 10 Pro

In attachment, I also send the UCF file of my design for the DDR3

Best regards,

Maxime

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11 Replies
satguy
Explorer
Explorer
1,026 Views
Registered: ‎04-19-2018

 

Did you use the MIG GUI and passed its check?

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1,015 Views
Registered: ‎09-23-2019

Hello,

Yes, I used the MIG GUI and the check pin selection generate an error that I can't understand.

Maxime 

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drjohnsmith
Teacher
Teacher
994 Views
Registered: ‎07-09-2009

One thing worries me
you say your using Vivado, and you have a UCF file,
Vivado uses an XDC file format

Me thinks something is wrong there
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930 Views
Registered: ‎09-23-2019

Hi,

The UDF file is generated at the "Pin Selection" step in the MIG configuration

Maxime

MIG7_PinSelection_Step.png

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kren
Moderator
Moderator
875 Views
Registered: ‎08-21-2007

Please let me know the FPGA part and package. I'll check.

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871 Views
Registered: ‎09-23-2019

Hello,

Thank you for your reply. I'm using an Artix7 XC7A35T-1CSG325C.

I've seen that when I put DDR3_CK on T3, the validatation succeed.But, this constraint was not present on UG586 and my board has already been designed. So my question is, if I put DDR3_CK on T3 in the MIG configuration and then put DDR3_CK on T2 (has designed on the PCB), is it OK ?

Thanks

Maxime

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kren
Moderator
Moderator
833 Views
Registered: ‎08-21-2007

The ddr3_odt[0] is placed on R6 which is not memory byte group pin (not in T0, T1, T2 or T3), but adjacent to T3. When T3 is for address/control signal and CK is included, it will pass the pinout rules, just as the error message told. 

The pinout with IP wizard should match with the board layout. If not, the memory controller cannot work normally.

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826 Views
Registered: ‎09-23-2019

Hi Kren and thanks for this reply.

I don't need speed for the DDR3 and I understand the MIG will not work normally but will it still work ?

Maxime

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kren
Moderator
Moderator
824 Views
Registered: ‎08-21-2007

No, it can't work, because the calibration will get failed.

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drjohnsmith
Teacher
Teacher
806 Views
Registered: ‎07-09-2009

Can I ask,

you say "this constraint was not present on UG586"

As I understand , UG586 has not been updated for years. Is this a new constraint that should be added to UG586 ?
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kren
Moderator
Moderator
798 Views
Registered: ‎08-21-2007

You can find this rule in "bank and pin selection guides for DDR3 designs" in ug586. You can find the lastest version at: https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf

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