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Explorer
Explorer
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Registered: ‎04-06-2017

DDR3 Read

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I debug DDR3 Read operation on chip. The result is shown in the following figure. I find sometimes app_rd_data updates every clock, sometimes every two clocks. Is this normal? When the data is updating, the write operation is conducted to the MIG app interface, will this cause problem? Thank you.

debug.jpg

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: DDR3 Read

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It is normal. It's valid user read data output from one address when app_rd_data_valid is high for one clock cycle. 

It's ok when read out data is valid meanwhile the user commands are issued to the MIG app interface.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: DDR3 Read

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have you compared this to the reference design generated when you made the IP

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Xilinx Employee
Xilinx Employee
240 Views
Registered: ‎08-21-2007

回复: DDR3 Read

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It is normal. It's valid user read data output from one address when app_rd_data_valid is high for one clock cycle. 

It's ok when read out data is valid meanwhile the user commands are issued to the MIG app interface.

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