02-19-2019 07:59 AM
Hi to All,
I want to discover the PL-PS AXI address mapping to the DDR4 controller address lines, the bank groups, banks, rows, and so on. My device is Zynq US+ MPSoC.
How can I obtain that?
02-20-2019 04:03 PM - edited 02-20-2019 04:04 PM
You want... what?
Are you looking for the mapping of AXI (byte) address bits to PSU DDR4 controller address lines?
The lower address bits are somewhat determined by you when you configure the PS DDR:
The upper-most address bits (rank & bank group) are fixed by the DDR controller:
02-21-2019 12:07 AM
Hi @jg_bds ,
Thank you for your reply.
Yes, I was looking for what you replied. I actually looked through DDRC register space and specifically ADDRMAP0-11 which are for memory address mapping.
Through the registers, it is possible to change the location of all bits including rank, bank-group, bank, and so on, while it seems through Zynq US+ MPSoC IP parameter setting we cannot do that for all the fields.
But I have another question :).
My memory module is DDR4 memory and in order to improve the throughput in DDR4, it is better to switch between different bank-groups in a ping-pong scheme. That means the location of bank-group bits should be in the lowest bits. Based on the ADDRMAP0-11 the current configuration is (row | bank | bank-group | column) and for that, the location of bank-group and column should be swapped. Am I thinking right?
02-21-2019 08:30 PM - edited 02-21-2019 08:31 PM
Not an answer to your question, but I did find it interesting that (non-Xilinx) DDR RAM controllers often don't have a simple map between "CPU" address lines and the RAM address lines. In fact, some controllers will hash the addresses using XORs to improve performance (for certain RAM access patterns).
This mapping can be reverse engineered using software-based timing methods. This 2016 Usenix paper has some details. In particular, pages 15-17 show the mappings for two Intel and one Samsung controller. The paper then goes on to demonstrate how knowledge of this mapping can be used for covert CPU<->CPU communications through timing of accesses to a shared RAM, but that's getting even further off topic.