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jojowi
Visitor
Visitor
917 Views
Registered: ‎04-28-2020

DDR4 DQS Gate Status Fail

Hello,

I got some Problems with the MIG on my Alveo U280 FPGA.

I have a custom design which uses the AXI-Interface of the MIG to continously write to random addresses. After some time the MIG "resets" (Output init_calib_complete goes to low and the MIG recalibrates) and the MIG Dashboard in the Hardware Manager shows the Message "FAIL: underflow of the coarse taps used for tracking. Error found on Rank 0, Byte 9." for the field "DQS Gate Status". There seems to be some fluctuations at which point this failure occurs: If I e.g. run this for 1000 cycles the failure occurs only in some cases, for 10000 cycles it occurs most of the time, ....

 

I already tried to reproduce this using the MIG Example Design. Using the example design there was a similar issue, but the effects were a bit different: Sometimes there was the same failure as with my custom design, sometimes it failed at differing stages of the re-calibration afterwards. And sometimes there was no failure at all. After some searching I found this to be the issue described in AR#73068: https://www.xilinx.com/support/answers/73068.html
Unfortunately the patch provided in the AR did not work for me (maybe a problem with the AU280?). But I was able to fix it by just overwriting the Multi-Cycle-Constraints in the MIG that cause this issue:

set_multicycle_path -setup -from [get_pins -hierarchical -filter {NAME =~ *C && PARENT_CELL =~ *mem_intfc/u_ddr_cal_top/calDone*}] -to [get_pins -hierarchical -filter {NAME =~ *mem_intfc/u_ddr_mc/bgr[*].u_ddr_mc_group*}] 1

 With this constraint the MIG Example Design is working reliably.

 

However this did not help with my custom design, there is still the same problem. So I assume the issue with my design is either a different issue than the issue with example design or another "version" of the same issue which isn't covered by this constraint.
The Configuration of the MIG in my custom design is the same as in the example design, the sys_clk and sys_rst are also connected in the same way.

Did somebody have a similar issue and/or a suggestion what might be causing this? Any help is appreciated!
Kind regards
Johannes

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3 Replies
deepalir
Xilinx Employee
Xilinx Employee
776 Views
Registered: ‎02-21-2019

Hi @jojowi 

Swapped DQS pairs can definitely cause DQS gate to fail. Have you checked your schematic to ensure it is in order? 

Also, you can use the Debugging guide in PG150 Starting on Pg 597. DQS Gate Calibration Failure is described on Pg 611 onward. 

kren
Moderator
Moderator
750 Views
Registered: ‎08-21-2007

After the patch (in AR#73068) is installed, you should recreate the DDR4 IP, regenerate the IP example design and then test it again on hardware.

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kshimizu
Xilinx Employee
Xilinx Employee
732 Views
Registered: ‎03-04-2018

Hello @jojowi ,

 

AR#73068 is for the post calibration data error, that means calibration itself always passes.  DQS gate tracking means it is one of VT tracking in the PG150. Note that it does not mean the DQS gate during the calibration.

 

I’m not sure why you overwrite the “set_multicycle_path” to the XDC.  The Patch removers that “set_multicycle_path”, and adds pipeline in the RTL instead.

 

Please check the XSDB and PG150 to get the root case.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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