DDR4 Read Data Error

[akhtar2510]

Hello guys

I use Xilinx VCU108 EV board , i want to write 240 x 640bit data in DDR4 memory and then read it. but i have error when i want to read data.

i send 240 address , read command and c0_ddr4_app_en = '1'  when c0_ddr4_app_rdy = '1' but i receive less than 240 data valid

normally i receive 230 to 238 data valid.

please help me to solve it.

thank you 

[calebd]

Hello @akhtar2510 

Can you provide a waveform of what you are seeing?

Are you expecting the commands to return in a certain time?  You may have hit a required command in between your reads that needs to be completed prior to handling your read requests.

[akhtar2510]

Dear ,

I use DDR4 clock out (300 MHz) . I receive data from BRAM (input Clock 600MHz) and then write to DDR4. I attached Write Program. please first check Write Program , because i guess i have problem in read and write

   cmd_en                                                                                                       <=  c0_ddr4_app_rdy;                                          // 1 clock delay app ready
    if (Start_write = '1') then
         RAM_RE                                                                                              <= '1';                                                                    // Enable BRAM IPcore
         RAM_RADD                                                                                        <= std_logic_vector(RAM_Address_write);           // BRAM read Address
         if (c0_ddr4_app_rdy = '1' and cmd_en = '1') then
            Command_counter                                                                              <= Command_counter + to_unsigned(1,9);
            c0_ddr4_app_addr                                                                             <= "00000"&Sampled_Line&std_logic_vector(Command_counter)&"000";
            c0_ddr4_app_cmd                                                                              <= "000";                                                            // write command
            c0_ddr4_app_en                                                                                 <= '1';     
         end if;
         if (c0_ddr4_app_wdf_rdy = '1'   and write_Counter <= Command_counter  ) then
            c0_ddr4_app_wdf_data                                                                        <= RAM_RData;                                            // write data from BRAM to DDR4
            c0_ddr4_app_wdf_wren                                                                        <= '1';
            c0_ddr4_app_wdf_end                                                                         <= '1';
            write_Counter                                                                                       <= write_Counter + to_unsigned(1,9);
            RAM_Address_write                                                                           <= RAM_Address_write + to_unsigned(1,8);
          end if;
        if (RAM_Address_write > to_unsigned(80,8)) then
            Start_write                                                                                           <= '0';
             Start_Read                                                                                         <= '0';
            Command_counter                                                                              <= (others => '0');
            RAM_Address_write                                                                           <= (others => '0');
            write_Counter                                                                                     <= (others => '0');
        end if;
   
    end if;

[calebd]

@akhtar2510 

I believe a waveform will allow me to see what is going on, and what your specific issue is.  From the code, it is difficult to debug and visualize the problem you are having.

What do you mean by you only receive a certain amount of writes back?  Are you sure the full testbench in simulation/hardware has run long enough?  Do you have a testbench for this behavior to run in simulation, or is this running on hardware?

[akhtar2510]

Dear ,

i send you test file and ILA simulation

please check and help me

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/02/2019 05:23:02 PM
-- Design Name:
-- Module Name: Main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Main is
 Port (
   c0_sys_clk_p                                                                          : in  std_logic;
  c0_sys_clk_n                                                                          : in  std_logic;
  c0_ddr4_act_n                                                                         : out  std_logic;
  c0_ddr4_adr                                                                           : out  std_logic_vector(16 downto 0);
  c0_ddr4_ba                                                                            : out  std_logic_vector(1  downto 0);
  c0_ddr4_bg                                                                            : out  std_logic_vector(0  downto 0);
  c0_ddr4_cke                                                                           : out  std_logic_vector(0  downto 0);
  c0_ddr4_odt                                                                           : out  std_logic_vector(0  downto 0);
  c0_ddr4_cs_n                                                                          : out  std_logic_vector(0  downto 0);
  c0_ddr4_ck_t                                                                          : out  std_logic_vector(0  downto 0);
  c0_ddr4_ck_c                                                                          : out  std_logic_vector(0  downto 0);
  c0_ddr4_reset_n                                                                       : out  std_logic_vector(0  downto 0);
  c0_ddr4_dm_dbi_n                                                                      : inout  std_logic_vector(9  downto 0);
  c0_ddr4_dq                                                                            : inout  std_logic_vector(79  downto 0);
  c0_ddr4_dqs_c                                                                         : inout  std_logic_vector(9  downto 0);
  c0_ddr4_dqs_t                                                                         : inout  std_logic_vector(9  downto 0)
 
 
  );
end Main;

architecture Behavioral of Main is
component ila_0
PORT (
    clk : IN STD_LOGIC;
    probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe6 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    probe7 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    probe8 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    probe9 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    probe10 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    probe11 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    probe12 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    probe13 : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
    probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
end component;
component ddr4_0 port (
-- Physical connection
sys_rst                                                                 : in  std_logic;
c0_sys_clk_p                                                            : in  std_logic;
c0_sys_clk_n                                                            : in  std_logic;
c0_ddr4_act_n                                                           : out  std_logic;
c0_ddr4_adr                                                             : out  std_logic_vector(16 downto 0);
c0_ddr4_ba                                                              : out  std_logic_vector(1  downto 0);
c0_ddr4_bg                                                              : out  std_logic_vector(0  downto 0);
c0_ddr4_cke                                                             : out  std_logic_vector(0  downto 0);
c0_ddr4_odt                                                             : out  std_logic_vector(0  downto 0);
c0_ddr4_cs_n                                                            : out  std_logic_vector(0  downto 0);
c0_ddr4_ck_t                                                            : out  std_logic_vector(0  downto 0);
c0_ddr4_ck_c                                                            : out  std_logic_vector(0  downto 0);
c0_ddr4_reset_n                                                         : out  std_logic_vector(0  downto 0);
c0_ddr4_dm_dbi_n                                                        : inout  std_logic_vector(9  downto 0);
c0_ddr4_dq                                                              : inout  std_logic_vector(79  downto 0);
c0_ddr4_dqs_c                                                           : inout  std_logic_vector(9  downto 0);
c0_ddr4_dqs_t                                                           : inout  std_logic_vector(9  downto 0);

-- Debug signals
c0_init_calib_complete                                                  : out  std_logic;
addn_ui_clkout1                                                          : out  std_logic;
addn_ui_clkout2                                                          : out  std_logic;
c0_ddr4_ui_clk_sync_rst                                                 : out  std_logic;
dbg_clk                                                                 : out  std_logic;
--user interface ports
c0_ddr4_app_addr                                                        : in  std_logic_vector(27  downto 0);
c0_ddr4_app_cmd                                                         : in  std_logic_vector(2  downto 0);
c0_ddr4_app_en                                                          : in  std_logic;
c0_ddr4_app_hi_pri                                                      : in  std_logic;
c0_ddr4_app_wdf_end                                                     : in  std_logic;
c0_ddr4_app_wdf_wren                                                    : in  std_logic;
c0_ddr4_app_wdf_data                                                    : in  std_logic_vector(639  downto 0);
c0_ddr4_app_wdf_mask                                                    : in  std_logic_vector(79  downto 0);

c0_ddr4_app_rd_data                                                    : out  std_logic_vector(639  downto 0);
c0_ddr4_app_rd_data_end                                                : out  std_logic;
c0_ddr4_app_rd_data_valid                                              : out  std_logic;
c0_ddr4_app_rdy                                                        : out  std_logic;
c0_ddr4_app_wdf_rdy                                                    : out std_logic;

dbg_bus                                                                : out std_logic_vector(511  downto 0)
);
end component;
signal       c0_init_calib_complete                                      : std_logic                                       := '0';
 signal       c0_ddr4_ui_clk1                                              : std_logic                                       := '0';
 signal       c0_ddr4_ui_clk2                                              : std_logic                                       := '0';
 signal       c0_ddr4_ui_clk_sync_rst                                     : std_logic                                       := '0';
 signal       dbg_clk                                                     : std_logic                                       := '0';
 signal       c0_ddr4_app_addr                                            : std_logic_vector(27  downto 0)                  := (others => '0');
 signal       Test_app_addr                                            : std_logic_vector(27  downto 0)                  := (others => '0');
 signal       c0_ddr4_app_cmd                                             : std_logic_vector(2  downto 0)                   := (others => '0');
 signal       Test_cmd                                             : std_logic_vector(2  downto 0)                   := (others => '0');
 signal       c0_ddr4_app_en                                              : std_logic                                       := '0';
 signal       c0_ddr4_app_hi_pri                                          : std_logic                                       := '0';
 signal       c0_ddr4_app_wdf_end                                         : std_logic                                       := '0';
 signal       c0_ddr4_app_wdf_wren                                        : std_logic                                       := '0';
 signal       c0_ddr4_app_wdf_data                                        : std_logic_vector(639  downto 0)                 := (others => '0');
 signal       c0_ddr4_app_wdf_mask                                        : std_logic_vector(79  downto 0)                  := (others => '0');
 signal       c0_ddr4_app_rd_data                                         : std_logic_vector(639  downto 0)                 := (others => '0');
 signal       c0_ddr4_app_rd_data_end                                     : std_logic                                       := '0';
 signal       c0_ddr4_app_rd_data_valid                                   : std_logic                                       := '0';
 signal       c0_ddr4_app_rdy                                             : std_logic                                       := '0';
 signal       c0_ddr4_app_wdf_rdy                                         : std_logic                                       := '0';
 signal       dbg_bus                                                     : std_logic_vector(511  downto 0)                 := (others => '0');
 signal       State                                                       : std_logic                                       := '0';
 signal       Write_en                                                       : std_logic                                       := '0';
 signal       cmd_en                                                        : std_logic                                       := '0';
 signal        Command_counter                                               : unsigned (9 downto 0)                           := (others => '0'); 
 signal       Test_App_en                                             : std_logic                                       := '0';
 signal       Test_App_We                                             : std_logic                                       := '0';
 signal       Pre_Address_flag                                            : std_logic                                       := '0';
 signal       Post_Address_flag                                            : std_logic                                       := '0';
 signal       RAM_Address                                                  : unsigned (9 downto 0)                           := (others => '0'); 
  signal       Pre_Counter                                                 : unsigned (9 downto 0)                           := (others => '0'); 
  signal       Test_wdf_data                                                 : std_logic_vector (9 downto 0)                           := (others => '0'); 
 signal        post_Counter                                                 : unsigned (9 downto 0)                           := (others => '0'); 
   signal       RAM_Data                                        : std_logic_vector(639  downto 0)                 := (others => '0');

begin
ILA: ila_0
PORT MAP (
    clk                                                              => c0_ddr4_ui_clk1 ,
    probe0(0)                                                        => Test_App_en,
    probe1(0)                                                        => Test_App_We,
    probe2(0)                                                        =>c0_ddr4_app_wdf_rdy ,
    probe3(0)                                                        => c0_ddr4_app_rdy,
    probe4(0)                                                        => Pre_Address_flag,
    probe5(0)                                                        => Post_Address_flag,
    probe6                                                         => Test_cmd ,
    probe7                                                         => Test_wdf_data ,
    probe8                                                         => c0_ddr4_app_rd_data(9 downto 0),
    probe9                                                         => std_logic_vector(Pre_Counter),
    probe10                                                        => std_logic_vector(Post_Counter),
    probe11                                                        => std_logic_vector(RAM_Address),
    probe12                                                        => std_logic_vector(Command_counter),
    probe13                                                        => Test_app_addr ,
    probe14(0)                                                        => state,
    probe15(0)                                                        => c0_ddr4_app_rd_data_valid
);
DDR4_MIG : ddr4_0 port map (
sys_rst                                                                => '0'                            ,
c0_sys_clk_p                                                           => c0_sys_clk_p                   ,
c0_sys_clk_n                                                           => c0_sys_clk_n                   ,
c0_ddr4_act_n                                                          => c0_ddr4_act_n                  ,
c0_ddr4_adr                                                            => c0_ddr4_adr                    ,
c0_ddr4_ba                                                             => c0_ddr4_ba                     ,
c0_ddr4_bg                                                             => c0_ddr4_bg                     ,
c0_ddr4_cke                                                            => c0_ddr4_cke                    ,
c0_ddr4_odt                                                            => c0_ddr4_odt                    ,
c0_ddr4_cs_n                                                           => c0_ddr4_cs_n                   ,
c0_ddr4_ck_t                                                           => c0_ddr4_ck_t                   ,
c0_ddr4_ck_c                                                           => c0_ddr4_ck_c                   ,
c0_ddr4_reset_n                                                        => c0_ddr4_reset_n                ,
c0_ddr4_dm_dbi_n                                                       => c0_ddr4_dm_dbi_n               ,
c0_ddr4_dq                                                             => c0_ddr4_dq                     ,
c0_ddr4_dqs_c                                                          => c0_ddr4_dqs_c                  ,
c0_ddr4_dqs_t                                                          => c0_ddr4_dqs_t                  ,
c0_init_calib_complete                                                 => c0_init_calib_complete         ,
addn_ui_clkout1                                                         => c0_ddr4_ui_clk1               ,
addn_ui_clkout2                                                         => c0_ddr4_ui_clk2               ,
c0_ddr4_ui_clk_sync_rst                                                => c0_ddr4_ui_clk_sync_rst        ,
dbg_clk                                                                => dbg_clk                        ,
c0_ddr4_app_addr                                                       => c0_ddr4_app_addr               ,
c0_ddr4_app_cmd                                                        => c0_ddr4_app_cmd                ,
c0_ddr4_app_en                                                         => c0_ddr4_app_en                 ,
c0_ddr4_app_hi_pri                                                     => c0_ddr4_app_hi_pri             ,
c0_ddr4_app_wdf_end                                                    => c0_ddr4_app_wdf_end            ,
c0_ddr4_app_wdf_wren                                                   => c0_ddr4_app_wdf_wren           ,
c0_ddr4_app_wdf_data                                                   => c0_ddr4_app_wdf_data           ,
c0_ddr4_app_wdf_mask                                                   => c0_ddr4_app_wdf_mask           ,
c0_ddr4_app_rd_data                                                    => c0_ddr4_app_rd_data            ,
c0_ddr4_app_rd_data_end                                                => c0_ddr4_app_rd_data_end        ,
c0_ddr4_app_rd_data_valid                                              => c0_ddr4_app_rd_data_valid      ,
c0_ddr4_app_rdy                                                        => c0_ddr4_app_rdy                ,
c0_ddr4_app_wdf_rdy                                                    => c0_ddr4_app_wdf_rdy            ,
dbg_bus                                                                => dbg_bus                       
);

c0_ddr4_app_en                                                                          <= c0_ddr4_app_rdy and (Write_en or (Pre_Address_flag and cmd_en));
Test_App_en                                                                          <= c0_ddr4_app_rdy and (Write_en or (Pre_Address_flag and cmd_en));
Test_App_We                                                                        <= c0_ddr4_app_rdy and Write_en ;
c0_ddr4_app_wdf_wren                                                                        <= c0_ddr4_app_rdy and Write_en ;
c0_ddr4_app_wdf_end                                                                         <= c0_ddr4_app_rdy and Write_en ;
 
process (c0_ddr4_ui_clk1)
begin
 if (rising_edge(c0_ddr4_ui_clk1)) then
         cmd_en                                                                                          <= c0_ddr4_app_rdy;
         Write_en                                                                                        <= '0';
    if (State = '0') then
         Write_en                                                                                        <= '1';
         if (c0_ddr4_app_rdy = '1' and c0_ddr4_app_wdf_rdy = '1') then
            Command_counter                                                                              <= Command_counter + to_unsigned(1,10);
            c0_ddr4_app_addr                                                                             <= "000000000000000"&std_logic_vector(Command_counter)&"000";
            Test_app_addr                                                                             <= "000000000000000"&std_logic_vector(Command_counter)&"000";
            c0_ddr4_app_cmd                                                                              <= "000";
            Test_cmd                                                                                      <= "000";
            c0_ddr4_app_wdf_data                                                                        <= std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter)&std_logic_vector(Command_counter);
            Test_wdf_data                                                                        <= std_logic_vector(Command_counter);
         end if;
         if ( Command_counter > to_unsigned(300,10)) then
         Command_counter                                                                                 <= (others => '0');
         State                                                                                           <= '1';
         Pre_Address_flag                                                                                           <= '1';
         Post_Address_flag                                                                                           <= '1';
         end if;
      
    end if;
 
  if (State = '1') then

if (c0_ddr4_app_rdy = '1' and Pre_Address_flag= '1' and cmd_en = '1') then
   c0_ddr4_app_addr                                                                            <= "000000000000000"&std_logic_vector(RAM_Address)&"000";
   Test_app_addr                                                                            <= "000000000000000"&std_logic_vector(RAM_Address)&"000";
   RAM_Address                                                                                 <= RAM_Address + to_unsigned(1,10);
   Pre_Counter                                                                                 <= Pre_Counter + to_unsigned(1,10);                                                                               
  c0_ddr4_app_cmd                                                                              <= "001";
  Test_cmd                                                                                      <= "001";
   end if;
 if (Pre_Counter > to_unsigned(299,10)) then
    Pre_Address_flag                                                                           <= '0';
 end if;
if (c0_ddr4_app_rd_data_valid = '1')  then
   RAM_Data                                                                                     <= c0_ddr4_app_rd_data;
   Post_Counter                                                                                 <= Post_Counter + to_unsigned(1,10);                        
 end if;

 if (Post_Counter > to_unsigned(290,10)) then
          RAM_Address                                                                                 <= (others => '0');
          Pre_Counter                                                                                 <= (others => '0');
          Post_Counter                                                                                 <= (others => '0');
    Post_Address_flag                                                                           <= '0';
    state                                                                                       <=  '0';
 end if;
  end if;

 
 
 
 
 end if;
 end process;

end Behavioral;

[calebd]

@akhtar2510 

From the data you provided, I do not see anything wrong and I cannot see where you are delineating between reads you are counting.  From the data in the ILA you have more than 240 reads going on in your system.  Please clarify on what exactly your issue is.

In terms of your code, I don't know what to debug since I don't know your issue.  Even if I did now the exact debug criteria, I don't believe I can just fix your code as I do not know the entire system.  For instance, one thing I noticed is you have the line where c0_ddr4_app_wdf_data is assigned with >20 instances of the same value and'd together.  That seems like a waste of logic, but maybe I am missing something in your overall design, or something else is going on.

[behnam_2705new · Accepted solution]

honestly, It's too hard for us to help you with this information. let me propose a new scenario for testing your read and write process on DDR with MIG IP core. 

code a counter than write the number of counter on DDR(one by one), then read the value of DDR(one by one) then check if the value match pass, if not capture this waveform for us than post it.

the best way for capturing is making a trig signal, if data doesn't match trig one signal then use this signal as your ILA trigger.

capture your waveform from ILA or in a simulation then post it as a reply.

please show us this signal on your waveform.

also, have a short review this website that I mention below

https://numato.com/kb/simple-ddr3-interfacing-on-neso-using-xilinx-mig-7/

c0_init_calib_complete

c0_ddr4_app_addr
c0_ddr4_app_cmd
c0_ddr4_app_en
c0_ddr4_app_hi_pri
c0_ddr4_app_wdf_end
c0_ddr4_app_wdf_wren
c0_ddr4_app_wdf_data
c0_ddr4_app_wdf_mask

c0_ddr4_app_rd_data
c0_ddr4_app_rd_data_end
c0_ddr4_app_rd_data_valid
c0_ddr4_app_rdy
c0_ddr4_app_wdf_rdy