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Newbie
Newbie
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Registered: ‎01-02-2019

DDR4 Vref training

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Hello,

I'm looking for detail information regarding Vref training for Ultrascale and UltrascalePlus products.

I understand, in PG150 documentation, that the Vref training is common to all lanes of a group of memories and that the MIG interface don't adjust per lane or DDR the Vref centering.

Am i wrong?

Best regards,

JY

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Moderator
Moderator
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Registered: ‎01-09-2019

Hello @jean-yves 

I am not sure of any location that describes Vref training in more detail for the MIG than in PG150 (UG1085 describes the procedure on the Zynq US+ PSDDR controller).

Regarding your question, I am not completely sure if I understand what you are asking so I can't completely say it is correct.  What I can say is that Vref training is I believe done on only one range.  My question would be, why are you asking for this information?  The Vref training is required for DDR4 and is enabled by default to be run.  If you are running into issues I would be looking at your data eye and do some signal integrity adjustments/measurements from there.

Thanks,
Caleb
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Moderator
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Registered: ‎01-09-2019

Hello @jean-yves 

I am not sure of any location that describes Vref training in more detail for the MIG than in PG150 (UG1085 describes the procedure on the Zynq US+ PSDDR controller).

Regarding your question, I am not completely sure if I understand what you are asking so I can't completely say it is correct.  What I can say is that Vref training is I believe done on only one range.  My question would be, why are you asking for this information?  The Vref training is required for DDR4 and is enabled by default to be run.  If you are running into issues I would be looking at your data eye and do some signal integrity adjustments/measurements from there.

Thanks,
Caleb
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