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Observer
Observer
539 Views
Registered: ‎04-23-2019

DDR4 command/address/clk reference plane routing

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Hi,

We are designing a board with the ZU5 US+ and Micron M40A512M16 DDR4 chips (not DIMMs).

I see some different guidelines from Micron and Xilinx about which plane the command/address/clk signals should be referenced to.

From Micron TN-40-40:

  • Designs should reference data bus signals to VSS.
  • CA bus and clock should reference VDD.

From Xilinx UG583:

22. For DIMMs, place bypass capacitors near the command/address/control pads to provide
extra ground via locations. In addition, the bypass capacitors also provide a lower
impedance path from power to ground, which is important because
address/command/control pins are referenced to ground on the FPGA and PCB, while
they are referenced to power on the DIMM.

 

Since we are using chips (not DIMMS), which plane should command/address/control be referenced?

Thanks,

Emmett

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Xilinx Employee
Xilinx Employee
506 Views
Registered: ‎03-14-2016

Hello Emmett,

For board mounted DRAMs devices, we recommend referencing ground.  If your stackup does not allow you to reference, you can reference VSS.  The main concern is that you don't change reference at some point on the board.

Thank you,
Sam

   

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Xilinx Employee
Xilinx Employee
507 Views
Registered: ‎03-14-2016

Hello Emmett,

For board mounted DRAMs devices, we recommend referencing ground.  If your stackup does not allow you to reference, you can reference VSS.  The main concern is that you don't change reference at some point on the board.

Thank you,
Sam

   

View solution in original post

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Observer
Observer
443 Views
Registered: ‎04-23-2019

Hi Sam,

Thanks for the reply.

Do you see any problem in routing on a signal layer between VDD and GND planes?

e.g. VDD above, GND below?

Thanks,

Emmett

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