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e.b
Newbie
Newbie
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Registered: ‎05-14-2019

DDR4 for Xilinx UltraScale+ XCZU11EG-2FFVB1517i

Hi,

Trying to figure out if Micron's DDR4 MT40A512M16LY-062E IT:E  can work with the Xilinx part UltraScale+ XCZU11EG-2FFVB1517i.

In Xilinx SW for the memory controller definition it is suggested to use the Micron P.N: MT40A512M16HA-075E which doesn’t exist.

Any way, this is an 075E grade speed (CL=18 cycles) while the MT40A512M16LY-062E IT:E part is 062E speed grade (CL=22 cycles).

From the datasheet Backward Compatibility table it looks like the 062E can support 075 but not 075E.

1.jpg

Can you please advise? will the FGPA work with this memory? (it is the suggested DDR4 from Micron for new designs).

Thanks

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garethc
Moderator
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Registered: ‎06-29-2011

Hi @e.b 

Is this the PS DDR or the PL MIG IP?

For Xilinx processing system memory solution using the PS DDR controller the max bandwidth is 2400Mb/s. Please see Table 30 of DS925 on Page 27. So using the -062E memory device derated to -075 speed bin would not be supported and this would be 2666Mb/s and the controller is not spec'd to that speed.

For our PL MIG you can go to 2666Mb/s with our -2 device. Please refer to Table 74 of DS925 on Page 48. So, using this -062E device and derating to -75 speed bin is ok and should work at the highest spec'd speed once all our PCB Guidelines are followed.

And yes the backward compatibility Table 154 does indicate that the -062E device is compatible with -075 speed bin and not the -075E speed bin.

 

 

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Gareth
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e.b
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Registered: ‎05-14-2019

Hi Gareth,

Thanks for your fast response.

The plan is to use the same x16 device for PS DDR and PL MIG.

I am trying to figure out what to do now.

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e.b
Newbie
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Registered: ‎05-14-2019

Hi Gareth,

I just want to add,

MT40A512M16LY-062E IT:E does not work at 2666 MT/s with CL=18.

The DS shows that is needs CL=19 (compatible with -75 speed grade) at 2666. Please see Table 154 above Backward Compatibility, and Table 161.

I hope there is a way for the controller to set the correct CL.

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e.b
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Registered: ‎05-14-2019

 No answer for me?

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ryana
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Registered: ‎11-28-2016

Hello @e.b ,

There are a few options here.

For the PL DDR controller there's something called the custom CSV flow where you can create a new memory part definition which will be imported in to the tools which will then generate all the timing parameters based on the information provided in the CSV file.  You can see this in AR#63462:
https://www.xilinx.com/support/answers/63462.html

Alternatively you can target the existing MT40A512M16HA-075E part in the tools and manually set the CAS Latency to 19.  The 'HA' part is functionally the same device as the 'LY' device but just a different package code.  WIth a CAS Latency of 19 and a CWL of 14 you're meeting the operating requirements of the -062E part at 2666Mbps.
Here you can see the different CAS Latency values from the drop down menu in the tools:
075E_cl_19.PNG

Here is the supported operating points for 2666Mbps and 2400Mbps for the -062E part:
cl_19_at_2666.png

For the PS DDR controller the maximum operating point is 2400Mbps and the lowest supported CAS Latency here is 17 with a CWL of 12, and that matches the DDR4 2400T preset:
ps_ddr_settings.png

I'm not sure if you're trying to target an existing design with the MT40A512M16HA-075E part with a CAS latency of 18, but if that's the case, then you'll have to buy the -062Y part if you want to have a drop in compatible replacement that doesn't require reconfiguring the IP.

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elhanan
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Registered: ‎08-22-2019

Hey Ryana


I'm using XCZU4 EG. My PS DDR Controller have 5 components configuration (the 5fth is for ECC) of
MT40A512M16JY-083EIT:B.


Recently we have been told that the MT40A512M16JY-083EIT:B is EOL and we should switch to:

MT40A512M16LY-062EAAT:EMy question is can i use it in my PS DDR Controller (with or without reconfiguring the IP)

BR

 

 

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