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dimitris78
Adventurer
Adventurer
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Registered: ‎09-13-2019

DDR4 memory simulation error

I am trying to simulate a design with DDR4 controllers and for that I need an external memory model. I used the code in the example design to extract the memory model, and then added it to the test bench along with the imports folder from the example design. The simulation is done in Vivado 2019.1.

While the example design works as expected, there is an error in the simulation. After a RD command I noticed half the DQS_t signals where High-Z when they should have had definite values.

The example design was generated for a Micron MTA4ATF51264HZ-2G6E1. Below is a screenshot of the error as well as the extracted code for DDR4 model.

2020-05-01 DDR4 debug - c0_ddr4_dqs_t signal is High-Z for 4 out of 8 pins.jpg
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kren
Moderator
Moderator
374 Views
Registered: ‎08-21-2007

When RD command is issued, the DQS signals are drivien by the DDR model. Please check the output of the model and the connections between DDR4 IP and DDR model.

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