cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
573 Views
Registered: ‎04-12-2018

DDR4 x4 byte enable

Hi,

I want to know if XIlinx DDR4 controller (Zynq MPSoC PL DDR4) in x4 mode support byte enable?       

And also what all limitation we have when we go with x4 instead of x8 in general.

Can someone help with this

0 Kudos
2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
501 Views
Registered: ‎08-21-2007

What do you mean by x4 byte? The burst length or the data width?

0 Kudos
Highlighted
Moderator
Moderator
412 Views
Registered: ‎11-28-2016

Hello @ryogitha ,

I'm not exactly sure what you mean by "Byte Enable" but there are no limitations with using x4 DDR4 devices with the PL DDR4 soft controller. There is an overall limitation that the IP can only support 9 discrete placements with Component interfaces so if you were using x4 devices then you'll only have a max data width of 36-bits. The other limitation is that there is no DM or DBI pin for x4 memory devices so you'll have to consider that in your system design for undersized accesses and the IP will not allow you to generate an AXI based design with x4 components.  DBI can be used to save power so if you were depending on that then it won't be available.

0 Kudos