03-26-2019 04:50 AM
I want to know if XIlinx DDR4 controller (Zynq MPSoC PL DDR4) in x4 mode support byte enable?
And also what all limitation we have when we go with x4 instead of x8 in general.
Can someone help with this
06-11-2019 09:31 AM
Hello @ryogitha ,
I'm not exactly sure what you mean by "Byte Enable" but there are no limitations with using x4 DDR4 devices with the PL DDR4 soft controller. There is an overall limitation that the IP can only support 9 discrete placements with Component interfaces so if you were using x4 devices then you'll only have a max data width of 36-bits. The other limitation is that there is no DM or DBI pin for x4 memory devices so you'll have to consider that in your system design for undersized accesses and the IP will not allow you to generate an AXI based design with x4 components. DBI can be used to save power so if you were depending on that then it won't be available.