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kaushik3105
Visitor
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Registered: ‎09-29-2014

Delayed run traffic generation

Hello,

 

I am running a MIG simulation of a DRAM MCB that is unaltered from the one generated by CoreGen and running the simulation of the example design using ISim. This MCB is based on Spartan6. Running pure functional simulation.

 

The Spartan6 memory interface solutions guide enumerates a couple of steps from the memory initialization to the traffic generation.

 

The brief steps are:

Memory Initialization:

1. data_mode_i is set to address pattern (0010), instr_mode_i is set to get the value from fixed_instr_i (which is set to WR or 000), and addr_mode_i is set to 011 for sequential address mode.

2. mode_load_i is asserted for one clock cycle

 

Traffic generation

1. addr_mode_i, instr_mode_i and bl_mode_i set to PRBS

2. run_traffic_i input is asserted.

 

From the attached waveform shot, the values of the data_mode, addr_mode and instr_mode change as per the steps. However, there ae a couple of things that are off:

1. It is my understanding that the memory initialization phase (before the mode_load_i signal is asserted) writes to the different addresses the data and prepares it for the traffic gen operation. Is this correct? If it is then from the waveform, you can observe mcb3_dram_a is tied to 0x0 suggesting otherwise.

2. when mode_load_i is asserted, run_traffic_i is also asserted. However, the change to addr_mode_i, instr_mode_i and bl_mode_i happen much later. In fact it happens when mode_load_i is reasserted. Why is that?

 

Looking forward to your responses.

 

Thanks,

Anirudh

issue1-delayed-run-traffic.PNG
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vsrunga
Xilinx Employee
Xilinx Employee
7,542 Views
Registered: ‎07-11-2011

Hi,

 

1. It is my understanding that the memory initialization phase (before the mode_load_i signal is asserted) writes to the different addresses the data and prepares it for the traffic gen operation. Is this correct? If it is then from the waveform, you can observe mcb3_dram_a is tied to 0x0 suggesting otherwise.

-- Yes, your undersatnding is correct, traffic gen parameters do not play any role until MCB  finishes its calibration

 

 

2. when mode_load_i is asserted, run_traffic_i is also asserted. However, the change to addr_mode_i, instr_mode_i and bl_mode_i happen much later. In fact it happens when mode_load_i is reasserted. Why is that?

--I hope changes will take effect only after calib_done signal is asserted, please check the transitions with respect to it.

 

 

Regards,

Vanitha

 

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kaushik3105
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Registered: ‎09-29-2014

Hi Vanitha,

 

As you can see, I have disabled the soft_calib_ip as I did not want to spend a significant time doing the calibration. Are you hinting the skipping the soft_calib_ip for functional simulation will result in some odd behavior?

 

 

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