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sambangi.ramesh
Visitor
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Registered: ‎11-27-2014

Designing appropriate Memory controller for specific DDR3 SDRAM

DDR3 memory controller :
 
I have taken a Block ram of size 256(width)x512, we send serially 256 write commands and accordingly 512 data items(256bit). We are able to see the corresponding signals at the DDR memory side. We read back this data and verified it with the contents of our Block RAM, it is working perfectly.

So i move to the next chunk of 256 commands. Here when i observed at the DDR side memory  signals the address are going on correctly, but the data sent is missing first two 256bit data items. I am not able to find the reason behind it.

 

User interface information:

app_addr width 28 bit.

ddr_DQ data bus width 72 bit

interface clock 200MHZ

DDR3 frequency is 400MHZ

for every address i am sending 512 bits (BC8 burst length)

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yenigal
Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Hi

 

Is this seen in simulation or hardware.

 

Can you upload the captures showing the issue to look at it and give you suggestions.

Regards,

Satish

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sambangi.ramesh
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Registered: ‎11-27-2014

This is happening in simulation

 

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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

I donot think data will be missing but suspect it might not be properly aligned.

Please cross check your app_* interface signal timings againt the ones given in UG586 command, write and read interface timing diagrams and make sure that max delay between command and corresponding write is not more than 2 clocks

 

Also visit below links for relavant discussions

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/can-there-be-1-or-2-empty-cycle-delay-between-two-halves-of-BL8/m-p/364047#M4380

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Mig-User-Interface-Back-To-Back-Timing/td-p/503861

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-DDR3-questions-about-delays-and-buffers-depthes/td-p/272216

 

 

Hope this helps

 

-Vanitha

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sambangi.ramesh
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Registered: ‎11-27-2014

hi,

 

I am also attaching screen shots of how RAM address and data changing at starting each write cycle.

 

during start of write cycle the RAM enable signal is asserted but address pointer increment is not  starting from zero

 

I am taking about the signals present in u_ui_top/ui_write_data/wdf_rdy_ns  , wr_data and rd_addr_w. 

 

 

 

1st write.png
2nd write.png
3rd write.png
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vsrunga
Xilinx Employee
Xilinx Employee
8,325 Views
Registered: ‎07-11-2011

Hi,

 

What is your Vivado Version and which simualtor is this?

Are you using MIG generated memory model and supported simulators ?

Can you send us your ready to simulate design for investigation or vcd wavs form dumps with all the required signals?

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