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doner_t
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Registered: ‎04-19-2016

Different video source to write PL DDR3 memory

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Hello,

 

I have two different video sources which are HDMI and Cameralink. I converts both interfaces to Axi4-Stream. Here are some questions : 

 

  • I want to be able to write both video source data to PL-side DDR3 memory. So, Should I use a Axi-Interconnect IP ? 
  • Should both Axi4-Stream interface clocks be the same ?
  • Should I use ui_clk  output of the MIG IP to drive these Axi4-Stream interfaces' clocks?
  • Should I two different VDMA IPs dedicated to each Axi4-Stream video source, to write/read  to/from  PL-side DDR3? 
  • Is there a reference design about the MIG IP with Zynq ? 

Best Regards,

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florentw
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Registered: ‎11-09-2015

Hi @doner_t

 

1.My basic HW check method is correct to control the accessibility of this PL side DDR3 in SDK ? 

> Yes this is correct

 

2.What could be possible reason of above error ? 

I can think about at least 3 things:

  • Is the zynq initialized? You can try to launch your application and then use mrd (without reseting the zynq)
  • Are you targeting the zynq? In xsct use targets to select the target. It needs to be the zynq
  • if nothing is working, could you try mrd -force...

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

Hi @doner_t,

 

  • I want to be able to write both video source data to PL-side DDR3 memory. So, Should I use a Axi-Interconnect IP ? 

> The best solution for video sources would be the VDMA IP.

 

  • Should both Axi4-Stream interface clocks be the same ?

> No you can use different clocks

 

  • Should I use ui_clk  output of the MIG IP to drive these Axi4-Stream interfaces' clocks?

> You can but you don't need to.

 

  • Should I two different VDMA IPs dedicated to each Axi4-Stream video source, to write/read  to/from  PL-side DDR3? 

> You have 2 choices: Use 2 VDMAs or use a single on creating a switch for the input stream. The only tricky part with the input switch is that you need to take care of switching only between frames.

 

  • Is there a reference design about the MIG IP with Zynq ? 

The xapp1285 shows a design with 2 video sources. It is close from what you want to do.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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doner_t
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Registered: ‎04-19-2016

Hello @florentw,

 

Thank you for your reply. 

 

I am currently using VDMAs as specified for following purposes in the attached simple block design ;

 

  • VDMA-1 : to write hdmi video data to the PL side DDR3 via MIG
  • VDMA-2 : to write cameralink video data to the PL side DDR3 via MIG
  • VDMA-3 : to read video data from PL side DDR3 via MIG

I always check the my hardware design before send it to Software developing over it. I basicly use a method for this check, that is looking at the accessibility to HW memories & registers in SDK, in a basic hello_world app. In this basic check, I can access the all axi-lite registers without any problem. I have used the 'mrd 'command to access to the addresses in XSCT window of SDK.  However, I can not access to the PL side DDR3 memories in SDK. I have reserved 1G for this memory in address editor, range from 0x4000_0000 to 0x7FFF_FFFF.  And an error is seen in XSCT window when I typing mrd 0x40000000 such that   ; memory read error at 0x40000000. Memory read aborted. External abort. 

 

Q:

  1. My basic HW check method is correct to control the accessibility of this PL side DDR3 in SDK ? 
  2. What could be possible reason of above error ? 

Best Regards,

design.JPG
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florentw
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3,906 Views
Registered: ‎11-09-2015

Hi @doner_t

 

1.My basic HW check method is correct to control the accessibility of this PL side DDR3 in SDK ? 

> Yes this is correct

 

2.What could be possible reason of above error ? 

I can think about at least 3 things:

  • Is the zynq initialized? You can try to launch your application and then use mrd (without reseting the zynq)
  • Are you targeting the zynq? In xsct use targets to select the target. It needs to be the zynq
  • if nothing is working, could you try mrd -force...

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

doner_t
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2,574 Views
Registered: ‎04-19-2016

Hello @florentw,

 

 

Thank you for your reply. 

 

I have tried to Zynq's memory test in SDK, for testing the PL side DDR3. Thank you. 

One next step is, I have to test whether the VDMA can write video data to PL-side DDR3.  Is there any reference design for this task ? ( Sw files )

 

Best Regards,

 

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florentw
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Registered: ‎11-09-2015

Hi @doner_t,

 

One next step is, I have to test whether the VDMA can write video data to PL-side DDR3.  Is there any reference design for this task ? ( Sw files )

> I don't think there is big changes. It should be mainly change the pointing address.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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