Disabling DDR on Zynq PS in old design

[davidfhorowitz@lmco.com]

Hello, 

I am working on porting a design that runs on a zc702 development board to a custom board.  The design was provided by Analog Devices for use with a zc702 development board to run their AD9361 transceiver. This is the guide that was followed:  https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl . On the development board everything works ok, but someone wasn't thinking when they designed the custom board and didn't include any external DDR memory. To get around this (for a demo), I need to disable the DDR memory in the PS. I've done this in the block diagram, however, doing this causes many implementation errors due to the main .v file being overwritten. I've tried to replace the overwritten .v file with the old version and manually commenting out any DDR related line, but that throws just as many errors. 

Is there any way to disable the DDR in the PS without it automatically removing the associated ports or overwriting the hdl files? 

Thank you for your time,

David 

[calebd]

davidfhorowitz@lmco.com 

What exact .v file are you seeing that is causing the issue?  Just to verify, this is an IPI/block design based flow, is that correct?

After generating output products it will update the hdl files and remove/add the required ports.  There isn't an option to not overwrite the files, after updating your design besides just not generating output products.  That would mean your configuration changes wouldn't come into place, and that would leave you at your original issue from what it sounds like.

Are you sure that DDR isn't necessary for the design?