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sasindugeemal
Observer
Observer
611 Views
Registered: ‎12-26-2019

Example design of Kintex UltraScale DDR4 memory controller timing failure

I am trying to run DDR4 example design on Xilinx Kintex Ultrascale XCKU060-1FFVA1517C device with a 8 GB SODIMM (from the existing device list). When I synthesis the example design Total Hold Stack (THS) fails. I need to figure out the reason behind it. I am driving the clock at 351 MHz. I have attached the screenshots of the error and the configurations.

 

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4 Replies
calebd
Moderator
Moderator
552 Views
Registered: ‎01-09-2019

Hello @sasindugeemal 

I ran the example design targetting your part, and do not run into any timing issues.  Can you provide your constraints in this design?  It seems like it may be possible that there is something conflicting between a constraint in your design.

Otherwise, can you try starting from scratch and creating the MIG example design by right-clicking on the IP .xci, and selecting "Open IP Example Design..."

Thanks,

Caleb


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sasindugeemal
Observer
Observer
536 Views
Registered: ‎12-26-2019

Hi @calebd ,

I tried the example design too. To figure out timing, after synthesis step, I clicked on report timing summary and ran it for default configuration and end up having THS violation. I am using vivado 2019.2

Thanks,

Sasindu 

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sasindugeemal
Observer
Observer
535 Views
Registered: ‎12-26-2019

I am attaching my constraints file below.

Thanks,

Sasindu

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kshimizu
Xilinx Employee
Xilinx Employee
445 Views
Registered: ‎03-04-2018

Hello @sasindugeemal ,

 

I think it is the same question as below.  I could not find out the same error with same settings.

https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/Example-design-of-DDR4-IP-has-timing-failures-on-Kintex/td-p/1159504

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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