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Explorer
Explorer
147 Views
Registered: ‎03-27-2017

How the AXI Datawidth Converter handles AXI IDs?

I noticed the slave interface of the AXI datawidth converter accepts transaction IDs but not the corresponding master interface. 

How then does the datawidth converter handle out-of-order transactions and outstanding transactions? I take it, with the MI not having an ID interface, transactions occur as they arrive?

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Xilinx Employee
Xilinx Employee
101 Views
Registered: ‎01-09-2019

Re: How the AXI Datawidth Converter handles AXI IDs?

@bfung 

Although a little older this AR describes what is going on: https://www.xilinx.com/support/answers/60009.html

It might be more useful to use the full AXI Interconnect in most cases than trying to use the various sub-IPs.  The AXI Interconnect and AXI SmartConnect are meant to utilize the IPs inside of them only when needed and to handle the interconnection between your Slaves and Masters.

Side note, in the future these types of AXI questions may be better suited for our Processor System Design forum: https://forums.xilinx.com/t5/Processor-System-Design/bd-p/EMBEDDED

Thanks,
Caleb
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