My VU37P board may meet DRAM_y_STAT_CATTRIP warning in a repeated power on and power off test. （Real device temp is around 20~30℃)。
I have tried to assert another reset command by APB_y_PRESET_N. But it can't reset the warning signal to Zero (It's reset value).
The power-on and power-off sequence can meet the datasheet.
This DRAM_y_STAT_CATTRIP signal can only be removed when the power is turned on again by my test.
So what is the reason why this signal is set ? No mention about it in the HBM ug.
PS: Sometimes the device die temperature read from XADC are of a big gap to the data read by JTAG in Vivado.
IT is still a question confuse me! Please Xilinx employee Answer this question !
HBM assert Cattrip signal, can't be cleared unless power off .