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808 Views
Registered: ‎01-24-2018

How to connect c1_sys_clk and c3_sys_clk with same oscillator in DDR3 MIG Controller of Spartan6

Hello , I have designed one PCB which contain two ddr3 chips and one spartan6 fpga, and when I try to use both ddr3 at same time, I faced a problem.

My board is designed as shown below:
One 25Mhz oscillator , one xc6slx45 fpga and two ddr3 (placed at bank1 and bank3) are on the board. The oscillator is connected to globle clock pin.

The VHDL code of project entity is here:
entity RAM_Pj01 is
PORT(
    CK25IN        :in STD_LOGIC;        -- 25MHz
        DDR3 PIN xxxxxxxxxx
        xxxxxxxxxxx
)
end entity


Firstly, I just create a mig controller of one ddr3 chips (bank1 for example) and I just connect CK25IN pin to the c1_sys_clk directly through portmap like this:

DDR_1    :    DDR3_BANK1 port map(
...xxxx
CK25IN,
...xxxx
)

Then I use the mig controller interface to read/write bank1 ddr3, it works correctly.
Similary I test bank3 ddr3 seperattely and it also works well.

----------------------------------------------------------------------------------------

Secondly, I try to one mig controller which contains two ddr3 at same time. After mig set up, I portmap CK25IN to c1_sys_clk and c3_sys_clk of mig controller interface signal , but when implementation,
the error of "CK25IN have driven multiple buffers" is shown.

Then I use BUFG like this:
CK24IN_iBUFG : iBUFG
   port map (
      O => CK25, -- Clock buffer output
      I => CK25IN  -- Clock buffer input (connect directly to top-level port)
   );
And I portmap CK25 to c1_sys_clk and c3_sys_clk, but the error still show.

After that, I try to use PLL to "copy" CK25 clk signal to two same clock signal:
PLL2525:PLL25to25 port map (CK25,ck25_1,ck25_3);
The frequency/phase/duty cycle of two pll ouput are same as the input clock.
Then I portmap ck25_1 to c1_sys_clk, and portmap ck25_3 to c3_sys_clk.
But there are new errors showing:

'DDR_1/memc1_infrastructure_inst/se_input_clk.u_ibufg_sys_clk' and BUFG
   'PLL2525/clkout1_buf' on net 'CK25_1' are lined up in series. Buffers of the
   same direction cannot be placed in series.

'DDR_3/memc3_infrastructure_inst/se_input_clk.u_ibufg_sys_clk' and BUFG
   'PLL2525/clkout2_buf' on net 'CK25_3' are lined up in series. Buffers of the
   same direction cannot be placed in series.


So , I have no idea how to connect c1_sys_clk and c3_sys_clk with single 25Mhz oscillator.
Could any one give me a cue please?
Thanks!

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2 Replies
Moderator
Moderator
768 Views
Registered: ‎02-11-2014

Re: How to connect c1_sys_clk and c3_sys_clk with same oscillator in DDR3 MIG Controller of Spartan6

Hey lizhong.wei1986@gmail.com,

 

Which specific S-6 are you using? I see you are using a xc6slx45, but what package do you have? There are specific clocking guidelines that need to be followed to share clock sources in S-6. UG388 talks about the Clocking Guidelines for the MCB. And UG385 has some "Special Cases" that need to be looked into for a S-6 design as well. Do you know if you are violating any of these guidelines?

 

Thanks,

Cory

 

 

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Xilinx Employee
Xilinx Employee
735 Views
Registered: ‎07-15-2008

Re: How to connect c1_sys_clk and c3_sys_clk with same oscillator in DDR3 MIG Controller of Spartan6

MCB1 and MCB3 are placed east and west so you need a manual edit under the infactructure module to do it.

if you use MCB1 and MCB3 at the same rate this becomes possible, otherwise you need to find a separate source clock.

From a single source clock and PLL, you can drive BUFPLLMCB for the east side and west side.

MCB design is generated with clock buffer, so if you place the sys_clk pin correctly, it does the clock routing all good.


Please also reference this AR.
https://www.xilinx.com/support/answers/36431.html


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