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611 Views
Registered: ‎04-13-2017

I/O standard of sys_clk for Kintex7 MIG

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Hello,

 

I am designing a board using XC7K325T. I assigned all DDR3 pins in one HP Bank (32), except sys_clk and ddr3_reset_n, and assigned sys_clk and ddr3_reset_n to another HP Bank (33). The VCCO of the two bank is 1.5V. However, I found the following error message.

 

error.png

 

UG586 describes the following for sys_clk.

 

"For DDR3 interfaces that have the memory system input clock (sys_clk) placed on CCIO pins within one of the memory banks, the MIG tool assigns the DIFF_SSTL15 I/O standard (VCCO = 1.5V) to the CCIO pins. Because the same differential input receiver is used for both DIFF_SSTL15 and LVDS inputs, an LVDS clock source can be connected directly to the DIFF_SSTL15 CCIO pins."

 

To fix this error, should I manually change the I/O standard of sys_clk to DIFF_SSTL15 on the xdc file?

Why doesn't MIG change it automatically?

 

Thanks. 

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Xilinx Employee
Xilinx Employee
670 Views
Registered: ‎08-21-2007

回复: I/O standard of sys_clk for Kintex7 MIG

Jump to solution

When system input clock is assigned in the same bank of DDR3 interface, DIFF_SSTL15 I/O standard will be set up by MIG IP. As you would like to locate it to another bank, please constraint it in your top xdc file. Otherwise, Vivado tool will set the default IO standard (1.8V) for it,

2 Replies
Xilinx Employee
Xilinx Employee
671 Views
Registered: ‎08-21-2007

回复: I/O standard of sys_clk for Kintex7 MIG

Jump to solution

When system input clock is assigned in the same bank of DDR3 interface, DIFF_SSTL15 I/O standard will be set up by MIG IP. As you would like to locate it to another bank, please constraint it in your top xdc file. Otherwise, Vivado tool will set the default IO standard (1.8V) for it,

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548 Views
Registered: ‎04-13-2017

回复: I/O standard of sys_clk for Kintex7 MIG

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Thanks kren.
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