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crisilc
Contributor
Contributor
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Registered: ‎03-15-2018

ISERDES DDR 1:4 Use with DQS

I have a design that uses ISERDESE3 in Kintex ultrascale. My design contains a source-synchronous DQ and DQS (strobe) coming from an external interface to FPGA. I am using ISERDESE3 to deserialize the data and I am using DQS as a CLK to ISERDESE3 module.  In the same design, I have an OSERDESE3 for driving external interfaces with DQ and DQS.

As per UG571, I need to connect CLKDIV. But since DQS is NOT a continuous clock, how can I connect CLKDIV port in ISERDESE3 and OSERDES3 for a DATA_WIDTH=4? And DQS direction can change during operations.

This is a fairly standard interface mechanism and hence I would appreciate it if a ready solution is provided. 
 
Thanks
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5 Replies
603 Views
Registered: ‎01-22-2015

But since DQS is NOT a continuous clock, how can I connect CLKDIV port in ISERDESE3...

As described in text near Fig 2-26 of UG571 (v1.12), BUFGCE_DIV can be used to create CLKDIV from the interface clock.  BUFGCE_DIV does not require that its input clock be continuous.

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crisilc
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Registered: ‎03-15-2018

Thanks for the reply. markg@prosensing.com 

But in the same image CLKDIV for OSERDESE3 is the same for ISERDESE3. As DQS is used for CLK its direction can change based on operations. While FPGA sends out data, DQS will be generated from an internal MMCM/PLL. And while receiving data from an external interface it's a different DQS. In that case, how can I keep ensure the same CLKDIV for ISERDESE3 and OSERDESE? 

When I tried the same vivado flags an error saying "ISERDESE3 CLKDIV, OSERDESE3 CLKDIV pin nets are NOT in the same clock"

My usage case will be similar to Fig2-29 with IOBUF for DQS. 'O' pin of IOBUF will be CLK for ISERDESE3 and 'I' pin of IOBUF will be from OSERDESE3. In this case, CLKDIV net is different for ISERDESE3 and OSERDESE3. How can I implement such a design?

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Registered: ‎01-22-2015

While FPGA sends out data, DQS will be generated from an internal MMCM/PLL. And while receiving data from an external interface it's a different DQS.

You are describing two different clock domains.  One domain is clocked by a send-clock (let's call it DQS_S) and the other domain is clocked by a receive-clock (let's called it DQS_R). 

 

...how can I keep ensure the same CLKDIV for ISERDESE3 and OSERDESE? 

Since ISERDESE3 is clocked by DQS_R and OSERDESE3 is clocked by DQS_S then ISERDESE3 and OSERDESE3 are operating in different clock domains.  You can use DQS_R and a BUFGCE_DIV set to divide-by-4 to create CLKDIV for ISERDESE3.  You cans use DQS_S and a separate BUFGCE_DIV set to divide-by-4 to create CLKDIV for OSERDESE3. 

 

Since the DQS clocks are gated (ie. not continuous) you will not be able to use an MMCM to produce CLKDIV from DQS.

kshimizu
Xilinx Employee
Xilinx Employee
526 Views
Registered: ‎03-04-2018

Hello @crisilc and markg@prosensing.com ,

 

The subject is DDR, but the question is about the Transceiver.  It is better to post to “Serial Tranciver” to get variable information.  This community is about the Memory Interface.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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crisilc
Contributor
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Registered: ‎03-15-2018

Thanks, markg@prosensing.com 

I have moved the post to the serial Transivers thread. I Will continue from there. 

@kshimizu