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cbonifassi
Visitor
Visitor
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Registered: ‎10-04-2019

Identification of failing byte on MIG DDR3

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Hello,

The calibration of the MIG implemented on my design failed at Read Per-bit Deskew. I have the following error message: No valid data found for a given bit in the nibble when running the de-skew pattern. Error found on Rank 0, Nibble 0, Bit 3.

I'm trying to identify which bit is the Bit 3. Using UG571 p156, I'm thinking Bit 3 is the 3rd bitslice of each nibble 0 of the FPGA bank.

Can someone validate or invalidate this ??

Thanks

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deepalir
Xilinx Employee
Xilinx Employee
921 Views
Registered: ‎02-21-2019

Hi @cbonifassi 

The nibbles reported in the hardware manager isn’t necessarily referring to the physical pins in your layout and these are only the Select I/O nibbles.

In order to correlate the nibbles to the DQS pair, open up the package pin view, and tally your DQS pair with the bank in use and associate it with lower and upper nibbles as shown in UG571 pg 156. 

Once you have identified the associated RXTX_BITSLICE - T0L and T0U, bit 3 of T0L (Nibble 0) will identify as the bit 3 of that DQS byte. 

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kshimizu
Xilinx Employee
Xilinx Employee
968 Views
Registered: ‎03-04-2018

Hello @cbonifassi ,

 

Please check the “General Checks” in PG150(page.593).  If you do not follow the guide line, please consider the IBIs simulations in advance.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

The next step is to read the “hardware Measurements” at the per-bit deskew.  Taking waveform is hard, but we can get clues where is the issue.

 

I think that bit-3 might be an issue, but it is better to see the whole design by checking the “General Checks” in advance.

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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pg150_general_check.PNG
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cbonifassi
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Registered: ‎10-04-2019

Hello @kshimizu 

Thanks for your answer but you don't answer my question. Maybe I didn't explain the problem quite well.

I'm working on a board (not design by Xilinx) with some hardware problems on the DDR we're using. I'm trying to find which bit is the source of the problem using the message error returned by the MIG. Once I'm able to do that, I'll be able to realize the necessary reparations on the board to have a functional DDR.

I hope my explanation will help understanding my question better.

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deepalir
Xilinx Employee
Xilinx Employee
922 Views
Registered: ‎02-21-2019

Hi @cbonifassi 

The nibbles reported in the hardware manager isn’t necessarily referring to the physical pins in your layout and these are only the Select I/O nibbles.

In order to correlate the nibbles to the DQS pair, open up the package pin view, and tally your DQS pair with the bank in use and associate it with lower and upper nibbles as shown in UG571 pg 156. 

Once you have identified the associated RXTX_BITSLICE - T0L and T0U, bit 3 of T0L (Nibble 0) will identify as the bit 3 of that DQS byte. 

-----------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-----------------------------------------------------------------------------------------------------------------

View solution in original post

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cbonifassi
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Visitor
867 Views
Registered: ‎10-04-2019

Hello @deepalir 

Thanks for your answer.

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bhavanithya
Adventurer
Adventurer
525 Views
Registered: ‎06-04-2019
Hello,

I am facing the same error with my DDR.
"No valid data found for a given bit in the nibble when running the de-skew pattern. Error found on Rank 0, Nibble 2, Bit 1".
Were you able to find the source of this problem?
Thanks,
Bhavanithya Thiraviaraja
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