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varun98cr7
Visitor
Visitor
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Registered: ‎05-27-2020

Interfacing the PL with input data from DRAM

I am done with programming the VHDL part of my project. It involves reading input data (16-bit pixel valus of an image) from the DRAM memory location and writing the denoised 16-bit pixel outputted by the PL back into the DRAM. I am done with the post implementation of my program code. So I need someone to kindly answer the following questions-

1. Taking into account the factor that I have not done any interfacing prior to this project,Is there a guide/ tutorial to go about with this?

2. How do I store the 16-bit input pixel values onto the DRAM (currently in a .txt file on the computer)?

3. Do i have to create IP blocks to interface the data from DRAM with PL?  If yes, then how to do I it?

Regards

Varun

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rpr
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Moderator
351 Views
Registered: ‎11-09-2017

Hi @varun98cr7 

Are you looking for 7series or ultrascale?

Xilinx provides Memory Interface Generator - MIG

7 series UG586 - 7 Series FPGAs Memory Interface Solution User Guide

Ultrascale  PG150 - UltraScale Memory Product Guide

MIG has user interface and optional AXI interface, detailed information provided in respective product guides, refer them.

Xilinx MIG provides example design with test bench, so you simulate it and check how user interface and ddr interface works.

Configure MIG IP, right click on IP and select open example design.

Regards
Pratap

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