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alangford
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Participant
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Registered: ‎06-15-2017

Interfacing to the 512bit AXI UI side of a DDR3 MIG controller

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Hi,

 

Im working on a design using the zc706 dev board (zynq 7000 series), targeting the SODIMM that's connected to the PL fabric. I've successfully configured the MIG and included the traffic generator and tried this out on the board.

 

Im now moving onto my actual design and have a few questions regarding how to interface to the AXI4 UI interface on the MIG:

 

The memory interface data width is 64bit; the PHY to MC clock ratio is 4:1, giving a UI data width of 512bit

 

I have a couple of questions that I hoped to get some help with:

 

  1. 512bit is very wide for the UI side. If I have an AXI master data width of 32 or 64bit that I wish to interface to the MIG, how do I handle the width difference?
    • Ive seen that I can chose a narrower AXI data width in the MIG GUI, but Im wondering if this is the best approach, and if it will have an impact on the achievable bandwidth?
  2. Eventually Ill have multiple sources and sinks that I need to connect to the MIG for using the external memory as a pooled resource of memory.
    • What type of interconnect should I use for arbitrating between these sources?
    • Do I need to handle this with multiple memory controllers connected to a common DDR3 interface?
    • How to I "partition" the memory space to ensure the various sources/sinks have access to non-overlapping regions of memory in the DDR3 device? Presumably by simply controlling the address range of each source/sink? Or is there more to it than that?
  3. Can anyone suggest a good Xilinx reference paper that describes an example application of using the MIG with PL DDR3?

 

Thanks in advance

 

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alangford
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Participant
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Registered: ‎06-15-2017

Thank you both for your replies, 

 

Ill use the AXI interconnect IP

 

 

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u4223374
Advisor
Advisor
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Registered: ‎04-26-2015

1 & 2: use an AXI Interconnect. This will allow a group of slaves to access the MIG, handle congestion, perform the width conversion, etc.

 

2c: it's up to you to ensure that the various blocks don't overwrite each others' RAM. There's no built-in memory protection to prevent that.

 

3: any reference designs for the Kintex and Artix boards (eg. KC705, AC701) will cover this, as they always use a MIG and PL DDR3.

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vemulad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi @alangford

 

For AXI data width it is recommended to use width of UI data bus for better performance. Using a smaller width invokes an Upsizer, which would spend clocks in packing the data.

 

You can refer to this XAPP on multi port memory controller https://www.xilinx.com/support/documentation/application_notes/xapp1164.pdf

 

 

Thanks,
Deepika.
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alangford
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Registered: ‎06-15-2017

Thank you both for your replies, 

 

Ill use the AXI interconnect IP

 

 

View solution in original post

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