11-01-2017 10:14 AM
Im working on a design using the zc706 dev board (zynq 7000 series), targeting the SODIMM that's connected to the PL fabric. I've successfully configured the MIG and included the traffic generator and tried this out on the board.
Im now moving onto my actual design and have a few questions regarding how to interface to the AXI4 UI interface on the MIG:
The memory interface data width is 64bit; the PHY to MC clock ratio is 4:1, giving a UI data width of 512bit
I have a couple of questions that I hoped to get some help with:
Thanks in advance
11-01-2017 05:05 PM
1 & 2: use an AXI Interconnect. This will allow a group of slaves to access the MIG, handle congestion, perform the width conversion, etc.
2c: it's up to you to ensure that the various blocks don't overwrite each others' RAM. There's no built-in memory protection to prevent that.
3: any reference designs for the Kintex and Artix boards (eg. KC705, AC701) will cover this, as they always use a MIG and PL DDR3.
11-01-2017 11:41 PM
For AXI data width it is recommended to use width of UI data bus for better performance. Using a smaller width invokes an Upsizer, which would spend clocks in packing the data.
You can refer to this XAPP on multi port memory controller https://www.xilinx.com/support/documentation/application_notes/xapp1164.pdf