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Visitor
Visitor
8,249 Views
Registered: ‎03-11-2014

Is this DDR3 setup possible with MIG / ARTIX 7?

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Hi,

 

According to some other forum posts & UG586, when using multiple DDR3 components on a single MIG generated controller, ALL address/control/clk signals  (including LDQx) excpet DQx are shared on the DDR3 components. Is this assumption correct?

Attached the setup I'm planning to implement - 2 x DDR3 x 16 to form a 32 bit wide memory block.

Any advice / feedback would be much appreciated.

 

Thanks, best regards

Mike

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Xilinx Employee
Xilinx Employee
13,762 Views
Registered: ‎07-11-2011

Hi,

 

When you select a X16 component and increase the Data witdth to 32, MIG assumes there are two X16 components, it shares all address and control signals but I think not Data strobes.

Please generate MIG for your set up and observe the pinout in user_design/par folder against yours

 

Hope this helps

 

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
13,763 Views
Registered: ‎07-11-2011

Hi,

 

When you select a X16 component and increase the Data witdth to 32, MIG assumes there are two X16 components, it shares all address and control signals but I think not Data strobes.

Please generate MIG for your set up and observe the pinout in user_design/par folder against yours

 

Hope this helps

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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Visitor
Visitor
8,242 Views
Registered: ‎03-11-2014

Hi,

 

Thanks again for your valuable help - indeed the pin assignment is already done by MIG, located in a seperate constraints file.

I was not aware of that, as I could not see any connections done in the main project ucf.

 

Thanks, best regards

Mike

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