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Visitor ajivs
Visitor
493 Views
Registered: ‎10-03-2018

Kintex 7 Schematic Review- Memory Interface

Hello,

Please help to review the schematics for DDR3 & NOR flash interface with XC7K160T-3FFG676.

 

Regards

Aji

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1 Reply
Moderator
Moderator
406 Views
Registered: ‎11-28-2016

Re: Kintex 7 Schematic Review- Memory Interface

Hello @ajivs,

The QSPIs look fine.

For the DDR3 I noticed you have the external VREF pins connected on the banks but you have your VRP/VRN resistors configured for 50-ohm trace impedances.  I just wanted to point out that if you're going faster than 1333Mbps then you should have 40-ohm traces and setup your VRP/VRN resistors for 40-ohm traces (80-ohm values).  If you're below 1333Mbps then double check your current layout to make sure they're targeting 50-ohm traces.

For the DDR3 clock I'm not sure why you have two types of termination.  Remove the 100-ohm across the FPGA output DDR3_CLK_P/N pins.  The correct termination is already done with the in-line resistors on the single ended components.