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Adventurer
Adventurer
9,796 Views
Registered: ‎03-02-2015

Limit for number of back to back write/read

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Hi,

 

Is there any limit to the number of address locations we can write at a time in ddr3 using MIG ?

 

Earlier i was writing 1500 address locations one after other,then waiting for 10 us & reading those 1500 locations back.But in this case i wasn't reading any values back.

 

So i changed my fsm in such a way that i only write 300 locations at once & reading them back.It works now.

 

Both of the above mentioned cases worked in simulation,but on board only the 300 write cycle one works.

 

 

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Adventurer
Adventurer
16,905 Views
Registered: ‎03-02-2015

With 1500, all the locations i read are zeros.

I'm using my own FSM

 

I can check dbg siganls like mux_rd_rise/fall foreven in my custom design or only in example designs ?

 

I remember running example_design into which i added app_* into ILA on my board & it was working fine even for 1500 addresses.

 

 

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Xilinx Employee
Xilinx Employee
9,750 Views
Registered: ‎08-16-2007

No, there shouldn't be a limit. You didn't disable the periodic reads or DRAM REFRESH/ZQCAL commands did you?

It may be helpful if you provided what FPGA, Memory Type, and version of Vivado and MIG IP you're using.

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Adventurer
Adventurer
9,736 Views
Registered: ‎03-02-2015

@criley

FPGA - Virtex 7,Memory - DDR3,MIG ip - MIG v2.3;Vivado - 2014.4;

 

So you are saying that i can write the entire DDR3 chip back to back in a single go & then read it back again in a single go after a while.

Theoretically it should be possible,but is it possible ?

 

 

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Xilinx Employee
Xilinx Employee
9,731 Views
Registered: ‎02-06-2013

Hi

 

No it is not possible to read and write the entire chip in a single go.

 

The refresh and periodic reads if doing continous writes still need to happen for the chip to retain data.

 

 

Regards,

Satish

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Xilinx Employee
Xilinx Employee
9,726 Views
Registered: ‎07-11-2011

Hi,

 

what you mean by single go? continous writes and reads with sinagle write or read command or multiple write/read commands?

 

As you have developed your own fsm I think you have gone through UG586 comamnd, write and read path timing digrams.

To write or read from memory through controller you need to specify app_addr for each command and make sure app_rdy is asserted.

 

You will be able to perform continuous writes or reads only when app_rdy is high.

Please refer below link for app_rdy low reasons and ways to improve your throughput.

http://www.xilinx.com/support/answers/36719.html

 

Hope this helps

 

-Vanitha

 

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Adventurer
Adventurer
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Registered: ‎03-02-2015

@vsrunga,@yenigal

 

Hi,

 

app_addr signal in UI side of MIG in my design is of the form STD_LOGIC_VECTOR(15 downto 0);

So probably DDR3 has (2^16 - 1) address locations.So by single go i meant writing into 2^16 address locations back to back following write timing cycle.But as Satish mentioned,i think it is not possible.

 

In my case i was writing into 1500 address locations back to back & after waiting for 10 us,i'm trying to read those 1500 back to back.

In doing so i'm following timing diagrams,waiting for app_rdy to be high etc....But in that case the data i'm reading back wass only "0000..00".

 

So i reduced the number from 1500 to 300 & i'm reading the data back correctly.

 

So is there a time limit, like some time after which it has to do refresh operations etc... ? 

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Xilinx Employee
Xilinx Employee
9,712 Views
Registered: ‎07-11-2011

Hi,

 

During refresh controller will pull app_rdy low, so you will be obviusly restricted to access DDR3, so there is no time limit.

Even for 1500 addresses,  if you respect app_rdy and data is written to FIFO only when app_wdf_rdy is high, command and address are aligned I do not think you should read zeros.

It is possible that FIFO is filled with zeros, or you are reading form unwrittem addresses, you can probe DQ bus using high quality scope to confirm if data is zero during write or read.

 

 

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Adventurer
Adventurer
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Registered: ‎03-02-2015

@vsrunga:

 

Hi,

 

I can see my desired data on the app_wdf_data signal,it is not "0000.....0" & only by changing number of addresses from 1500 to 300 without no change in RTL i'm reading my data back.

Probably some design issue,but what do you mean by high quality scope on DQ bus ? Using some probe to examine data on DQ bus ?

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Xilinx Employee
Xilinx Employee
9,702 Views
Registered: ‎07-11-2011

With 1500, do you see expected data on some locations or all read locations are zeros?

have you modified example design TG or your own FSM

Yes, please use scope with DDR3_wr, DDR3_CAS as trigger and monitor DQ diring write and read.

You can also insert chipschope and check dbg siganls like mux_rd_rise/fall for expected data

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Adventurer
Adventurer
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Registered: ‎03-02-2015

With 1500, all the locations i read are zeros.

I'm using my own FSM

 

I can check dbg siganls like mux_rd_rise/fall foreven in my custom design or only in example designs ?

 

I remember running example_design into which i added app_* into ILA on my board & it was working fine even for 1500 addresses.

 

 

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