03-04-2019 04:32 AM - edited 03-04-2019 04:34 AM
I am using Vivado 2018.2. I am working on ZCU102 board.
I have generated DDR4 SDRAM MIG (v2.2) for the Component memory module MT40A256M16GE-075E. I have selected 625 MHz as Memory Device Interface Speed. I have selected 125 MHz as Reference Input Clock Speed as I want to use CLK_125 from ZCU102 board.
The MIG will generate an internal 625/4 clock (4:1 ratio) ie 156.25 MHz. I want the MIG MMCM to generate 2 additional clocks 156.25 & 625. ie X & 4X clock. But for some reason, this MMCM is not allowing it.
For Clock 1, I want D factor of 2 but the minimum availabe is 3. Why is that. A normal MMCM instance template gives me the ability to generate (125 * 10) / (1 * 2) = 625 MHz. But this MIG MMCM isn't allowing that. MMCM_FOUTMAX value from AC/DC switching characteristic is also 667 MHz.
So, why is MIG MMCM not being able to generate 625 MHz if my Input Reference clock is 125 MHz
03-04-2019 09:46 PM
This MMCM generated within MIG IP is mainly for PHY and user interface clock. So the attributes are restricted. That's the difference from the other MMCMs in fabric outside MIG. You can create your own MMCM outside MIG and share the input clock for MIG.
03-05-2019 12:21 AM
Can you provide me with a source in the form of a document or AR which indicates in what way a MIG MMCM differs from a normal MMCM & what kind of restrictions are placed on MIG MMCM & why?
03-05-2019 06:58 PM
As you see in the IP wizard, for this MMCM, the attributes Multiplier (M) and Divider (D) have been fixed to 10 & 1. So you have only set the D1, D2... according to your requirement.
03-05-2019 09:12 PM
@krenYes, I see that M & D have been fixed & D1 to D4 have been given to me to choose. But my question was that I can't choose D1 value of 2, the min. value I can choose is 3. I wanted to know why was that the case.
You mentioned that MIG MMCM is special & different from normal MMCM. So I wan't to know why MIG MMCM doesn't allow D1 value of 2 for additional user clock generation. If this is a design contraint by Xilinx, please provide me with a source document. Otherwise, I have to assume its a design flaw.