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Visitor duc1100
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Registered: ‎12-16-2018

MIG 7 DDR3 - How to debug in Zynq block design flow?

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I'm trying to debug a MIG 7 DDR3 interface on a Zynq (xc7z100) with a PS7 block design.  I'd like to combine the debug logic in the MIG 7 example design with my PS7 block design.  The "Open IP Example Design ..." opens a new project and I don't know how to merge this new project with a PS7 block design project.

 

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Visitor duc1100
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Registered: ‎12-16-2018

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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Thanks for the reponse.


@kren wrote:

So it's a new designed board. I suggest you open IP example design on the PL DDR3. It is a stanlone project containing only the example DDR3 desgin. Using that, you can firstly identify whether it's related to hardware.


kshimizu has also pointed me in this direction.  I haven't brough up a Zynq FPGA without the PS7 subsystem and associated software.  Is there a design note or training video that can get me on the correct path for bring up just the Zynq PS7?

Thanks for the support!

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Xilinx Employee
Xilinx Employee
212 Views
Registered: ‎03-04-2018

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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Hello @duc1100 ,

 

I’m not sure you question, but I will try to answer.  From my understanding, you want to develop both Zynq(PS) and Memory interface(PL) on the Block Design.

Attached is the ZC706 based design.  Zynq(PS) and Memory interface(PL) are on the same Block Design.  Red rectangle shows the Memory interface(PL), and the other is the Zynq(PS).

 

In order to create that design, the easiest way to use the “open example project” when starting the vivado.

1:Select the “open example project”, “Bae Zynq”, and then “ZC706”.

2:An example design based on the Zynq(PS) is created.

3:Select the “Board”, and then add the DDR3 SDRAM to the Block Design.  Note that the DDR3 SDRAM means the PL DDR.

 

I hope it would be useful for you.

 

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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PS and PL.PNG
open.PNG
base zynq.PNG
zc706.PNG
Visitor duc1100
Visitor
187 Views
Registered: ‎12-16-2018

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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Thanks for the response.

I've been able to generate a Zynq design with the PL DDR3 MIG IP generated interface.  I proved the flow out on the zc706 eval board.  The problem is we're in the process of bringing up a Zynq design with the PL DDR3 MIG IP generated interface on a custom board.  On this new board the PL DDR3 output signal, init_calibration_complete, doesn't go high after reset is removed.  The Zynq is monitoring the signal and is timing out waiting for the PL DDR3 initialization to complete.

The PL DDR3 MIG generated interface in the block design doesn't have any debug signals visible like those available in the PL DDR3 example project that is generated by the "Open example design...".   The MIG documentation, ug586, uses these debug signals to identify interface issues and debug interface/board problems.  I'd like to build the Zynq design with a PL DDR3 interface that has these signals visible but when I try the PL DDR3 IP generator doesn't make any of these debug signals available.  It's a black box with just the init, lock and reset controls visible. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-04-2018

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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Hello @duc1100 ,

 

Let me summarize my understanding based on your question.

The issue is that the calibration does not get High at the PL DDR3 MIG IP on the customer board.  In your design, the Zynq checks the status the calibration signal.  At this moment, there is no debug signals in the PL DDR3 MIG IP when creating a Block Design in vivado, so it is difficult to find out the cause.

 

Is it correct?

 

If so, I’m thinking about followings;

-Does the calibration fail every time? or Does the calibration success once at 10times?

-Which kind of memory parts do you use?  Is the memory parts same as ZC706?

-Could you please design only PL DDR3 MIG IP from the “IP Catalog”, Not including the Zynq?  You can select the debug signals in the MIG GUI.

 

 

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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Xilinx Employee
Xilinx Employee
149 Views
Registered: ‎08-21-2007

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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So it's a new designed board. I suggest you open IP example design on the PL DDR3. It is a stanlone project containing only the example DDR3 desgin. Using that, you can firstly identify whether it's related to hardware.

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Visitor duc1100
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Registered: ‎12-16-2018

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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Thanks for the follow up response.  Answers to your question below.

-Does the calibration fail every time? or Does the calibration success once at 10times?

We haven't seen a case where the calibration succeeds but may not have tried enough.  We'll repeat several times to see if it ever passes.

-Which kind of memory parts do you use? Is the memory parts same as ZC706?

Different memory parts.  ZC706 uses SODIMM MT8JTF12864HZ-1G6G1 our custom board uses 4 stand alone MT41K256M16TW-107.   Both boards have a 64-bit memory interface with a 4:1 PHY to user clock ratio.  The ZC706 operates with a 200Mhz system clock that also supplies the 200Mhz reference clock and used to generate a 800MHz DDR clock.  Our custom board operates with a 133.33Mhz system clock which generates the 533Mhz DDR clock.  The 200Mhz reference clock is generated by the PL DDR PLL looped out of the DDR3 IP block back into the ref_clk_i input.  The closest divisor is 198Mhz which is within the +/-10Mhz spec for the reference clock.  The custom board supplies the DDR (DDR3L) with a 1.35V supply.  The MIG includes the MT41K256M16xx-107 in the memory part pulldown and seems to support the clocking scheme and low power setting.

-Could you please design only PL DDR3 MIG IP from the “IP Catalog”, Not including the Zynq? You can select the debug signals in the MIG GUI.

This makes sense.  I've been resisting removing the PS7 because I've never brought up a Zynq FPGA without a PS7 subsystem and associated software.  If you can point me to an applicatable design note or training video showing how to bring up just the Zynq PL without a PS7 subsystem, that would be very helpful.

Thanks again for the support!

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Visitor duc1100
Visitor
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Registered: ‎12-16-2018

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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Thanks for the reponse.


@kren wrote:

So it's a new designed board. I suggest you open IP example design on the PL DDR3. It is a stanlone project containing only the example DDR3 desgin. Using that, you can firstly identify whether it's related to hardware.


kshimizu has also pointed me in this direction.  I haven't brough up a Zynq FPGA without the PS7 subsystem and associated software.  Is there a design note or training video that can get me on the correct path for bring up just the Zynq PS7?

Thanks for the support!

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Visitor duc1100
Visitor
91 Views
Registered: ‎12-16-2018

Re: MIG 7 DDR3 - How to debug in Zynq block design flow?

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Meant to ask about bringing up a stand alone Zynq PL without the PS7.
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