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shahan.a
Participant
Participant
448 Views
Registered: ‎06-25-2019

MIG 7 Series DDR3 Caliberation failure

Hi,

I am trying to implement a MIG 7 series DDR3 in design for a KC705 evaluation board. While testing I am not able to read or write from DDR. I checked the 'init_calib_complete' signal from MIG IP and it was not going high. I tested the same design in another KC705 board and there the DDR3 worked fine(I was able to read and write from the DDR and 'init_calib_complete' signal from MIG IP and it went high). What could be the reason for calibration failure on the first board?

I checked AR# 45681 But I am not able to access the link to Xilinx Answer 45653 provided there. It gives 404: Page Not Found error. Could you provide a valid link?

I am using Vivado 18.2

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2 Replies
dgisselq
Scholar
Scholar
401 Views
Registered: ‎05-21-2015

@shahan.a,

This may or may not be related to your problem, but since I've now found and corrected this bug in several designs now this week let me offer it to see if it might be related ...

  1. Make sure your reset into the MIG core is registered on the incoming clock to the core.  One of the designs I debugged sent resetn = (por_counter[9:0] == 0) into the core.  This reset wire, however, is going into some asynchronous contexts, and you really don't want it glitching as it settles.
  2. Make sure your user design then uses the reset and clock coming out of the core, not going into it, when interacting with the core.
  3. I know I personally had a problem with the MIG core some time ago being misconfigured ... so you might want to check that as well.

No, I don't know where the answer record you are asking for got moved to.  Sorry.  I hope the thoughts above might help though.

Dan

 

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kdeshwal
Xilinx Employee
Xilinx Employee
355 Views
Registered: ‎11-12-2019

Hi @shahan.a ,

Please go through XTP196 .
The document includes step by step process of generating MIG Example Design for all the supported memory types for KC705 board.

Best Regards,
Kuldeep

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