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gvirbila
Explorer
Explorer
558 Views
Registered: ‎07-01-2013

MIG Cal Fails on Upgrade to Vivado 2020

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I upgraded my project from 2018.3 to 2020.2. I performed the usual 'Report IP Status', upgraded the IP, checked/validated block design, ran synthesis/implementation and generated bit file.

When programmed, the MIG Calibration now fails with message, 'Pattern not found on GT_STATUS, all samples were 1. Expecting to sample the preamble. Error found on Rank 1, Byte 0, Nibble 7.'

This is a consistent error. There was no major version change with core, 2.2 (Rev. 6) to 2.2 (Rev. 10).

Any idea of what happened? Suggestions on how to correct?

 

Vivado 2018.3Vivado 2018.3

Vivado 2020.2Vivado 2020.2

 

 

 

 

 

 

 

 

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rpr
Moderator
Moderator
546 Views
Registered: ‎11-09-2017

Hi @gvirbila 

Apply the attached patch and check the behavior. I believe the patch resolves the issue. if not, Instead of updating the design would it possible for you to create a design in Vivado 2020.2? based on your possibility. Core provides example design, right-click on memory IP(2020.2) and select open example design and see any improvements in calibration stages.

Regards
Pratap

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rpr
Moderator
Moderator
547 Views
Registered: ‎11-09-2017

Hi @gvirbila 

Apply the attached patch and check the behavior. I believe the patch resolves the issue. if not, Instead of updating the design would it possible for you to create a design in Vivado 2020.2? based on your possibility. Core provides example design, right-click on memory IP(2020.2) and select open example design and see any improvements in calibration stages.

Regards
Pratap

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kren
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Registered: ‎08-21-2007

Do you get any other warning message in tcl console of hardware manager?

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gvirbila
Explorer
Explorer
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Registered: ‎07-01-2013

Thank you for the quick response.

Vivado 2020.2 now launches with the window title 'Vivado 2020.2_AR75986' so I am assuming Vivado took to the patch.

Do I need to re-run synthesis/implementation? I will check the results before re-running. 

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gvirbila
Explorer
Explorer
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Registered: ‎07-01-2013

When should I be looking at the tcl console? During the build or while programming the device from the Hardware Manager?

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rpr
Moderator
Moderator
517 Views
Registered: ‎11-09-2017

HI @gvirbila 

After applying the patch you should regenerate the IP output products.

Then rerun the synthesis and implementation.

Regards
Pratap

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gvirbila
Explorer
Explorer
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Registered: ‎07-01-2013

Thanks Pratap. I have upgraded the MIG IP, now version 2.2 (Rev 75986), rerun synthesis and implementation, resulting in successful MIG calibration.

Vivado 2020.2Vivado 2020.2

 

 

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