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Contributor
Contributor
4,764 Views
Registered: ‎08-22-2007

MIG DDR/QDR ucf problems

In my design I have created a MIG instance with a QDRII and a DDR2 controller. I have added the .xco file to my project and I instantiate the component in my VHDL. However, when I try to generate the core I get the following error message:

 

A Core Generator generated file MIG/user_design/par/ddr2_sdram.ucf does not exist in the project directory

 

It seems as if ISE is looking for a specific ucf file for the DDR2 controller, which doesn't exist. There is a ucf file for the combined controller (mem_controller.ucf) which covers all pins from both DDR and QDR interface but ISE doesn't seem satisfied with this.

 

A possible workaround might be to use the generated VHDL-files instead of the .xco file and add the mem_controller.ucf file manually. Will this work or is there a better solution?

 

Regards

Johan

 

EDIT: I'm using ISE10.1 with SP3 (32bit)

Message Edited by riesbeck on 02-20-2009 06:22 AM
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Xilinx Employee
Xilinx Employee
2,725 Views
Registered: ‎08-16-2007

Hi Johan,

I know there were some problems with using the .xco for MIG in ISE with older version of ISE but I thought they were fixed.

I would recommend just adding in all the RTL and UCF. A lot of users require modifying the RTL clocking or reset structure and do this anyways.

Thanks,
Chris
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