In my design I have created a MIG instance with a QDRII and a DDR2 controller. I have added the .xco file to my project and I instantiate the component in my VHDL. However, when I try to generate the core I get the following error message:
A Core Generator generated file MIG/user_design/par/ddr2_sdram.ucf does not exist in the project directory
It seems as if ISE is looking for a specific ucf file for the DDR2 controller, which doesn't exist. There is a ucf file for the combined controller (mem_controller.ucf) which covers all pins from both DDR and QDR interface but ISE doesn't seem satisfied with this.
A possible workaround might be to use the generated VHDL-files instead of the .xco file and add the mem_controller.ucf file manually. Will this work or is there a better solution?