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Observer zohaib.khan
Observer
898 Views
Registered: ‎03-13-2018

MIG DDR2 Artix Read/Write out of sync

Hello everyone,

 

I hope someone can help as to where I might be missing something.

 

I am trying to use MIG Series 7 DDR2 IPCore for Artix 7 device. xc7a75tfgg676-2 with DDR2 device from Micron as MT47HXX-25E. I am writing every address as data into address from starting address from 0x000100 (27 bits) till ending address 0x000400. I have two issues. First I am getting repetitive data in a stream of synchronized data, for example for h128 to 1h58 and then certain data from address h3d0 or h3c8 and so on, which is completely unexpected. Secondly the data is also read twice , for example certain data is read twice from the memory rather than once, after a rd_data_valid signal is asserted low. I am attaching the screenshots from the ILA debug module. Hope someone can guide me in this context. will be very much appreciated. S1_Read.PNGS1_Write.PNGS2_Write.PNGS2_Write_Read.PNGS3_Read.PNGS5_Read.PNG

 

 

S1_Read.PNG
S1_Write.PNG
S2_Write.PNG
S2_Write_Read.PNG
S3_Read.PNG
S4_Read.PNG
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4 Replies
Moderator
Moderator
828 Views
Registered: ‎02-11-2014

Re: MIG DDR2 Artix Read/Write out of sync

Hell0 @zohaib.khan,

 

Are you receiving these results on a custom board? Are you seeing the same thing happen with our default IP Example Design? If not, I would suggest using the Example Design as a baseline and slowly add in a traffic pattern that looks more like your application to see if you can reproduce the issue with our IP.

 

Thanks,

Cory

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Observer zohaib.khan
Observer
803 Views
Registered: ‎03-13-2018

Re: MIG DDR2 Artix Read/Write out of sync

Hello Cory,

 

Thanks for your reply. I am seeing this on a custom board. I re-ran the design with the IP core, with this time 4:1 mode, and it worked surprisingly without any incorrect stream of packet or data in between synced data. This is strange as I expected the same behavior with a 2:1 mode. I initially did begin with the example design, first with simulation and then with the hardware testing. For now 4:1 mode works with my custom design and board, with the exception of 64 bit data width instead of 32 bit width. 

 

Also I came across some application notes from Xilinx involving timing and calibration issues with the 2:1 mode.

 

https://www.xilinx.com/support/answers/53435.html

https://www.xilinx.com/support/answers/47383.html

https://www.xilinx.com/support/answers/46487.html

https://www.xilinx.com/support/answers/52123.html

 

I just wanted to know whether its better to use the core in 4:1 mode or 2:1 mode for frequencies around 250-300 Mhz.? 

 

I look forward to your reply.

 

Thanks again

Zohaib 

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Moderator
Moderator
771 Views
Registered: ‎02-11-2014

Re: MIG DDR2 Artix Read/Write out of sync

Hello @zohaib.khan,

 

I am glad your application is mostly working with 4:1 mode.

 

Generally lower frequencies we recommend to use 2:1 mode as there is lower latency. Most of the AR's in reference are for ISE MIG core versions and not Vivado. All of them will be fixed in Vivado. Which version of the core/Vivado are you using?

 

Thanks,
Cory

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Observer zohaib.khan
Observer
751 Views
Registered: ‎03-13-2018

Re: MIG DDR2 Artix Read/Write out of sync

Hello Cory,

 

Its MIG Series version 4.0, with Vivado 2017.3. What do you recommend for frequencies around 250Mhz? 2:1 or 4:1 ? Moreover I posted another issue that I am having now with the 4:1 mode is testing in hardware for large memory spaces say from 0h0000 till 0h5000 or more and then reading back all, the memory reads back around 10 or 15 values after the starting reading address and also reads the same after the ending read address. It works fine with smaller memory spaces say from 0h0000 to 0h2000 or 0h1500 (all addresses 27 bits- I am writing the data as addresses in the memory for testing purposes), but for larger memories its failing? Any core options you can suggest (Fullstrength/ Reduced Strength or any other related options that I can tweak for correct operation with large memory spaces in 4:1 mode?

 

Looking forward to your reply

 

Thanks 
Zohaib

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