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Adventurer
Adventurer
9,055 Views
Registered: ‎12-25-2014

MIG DDR3 Memory Addressing confusion for Virtex 6 on ML605 kit

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I have to implement a DDR3 SDRAM SODIMM interfaced with Virtex 6 on ML605 kit. The DRAM device is MT4JSF6464H – 512MB. It is single rank.

The app_addr width is 27 which is composed of 1(Rank) + 3(Bank) + 13(Row) + 10(Column). So, it is single rank with 8 Banks, each bank having 8192 Rows, eack Row having 1024 Columns, each Column having 64 bits. Since it has x16 configuration, that means it has 4 components each having 16 bits.

So the total memory, 512 MegaBytes is formed by 1(Rank) x 8(Bank) x 8192(Row) x 1024(Column) x 64 bits = 4096 MegaBits. By converting to MegaBytes, 4096Mb/8 = 512 MB(MegaBytes).

Is my understanding of the memory addressing correct, specifically in that each Column has 64 bit storage capacity?

 

I was looking at this question where the user Bob Elkind answers the question stating that, if the data port width is 64 bits & for a burst length of 8, to perform continuous read/ write burts, one must increment app_addr by 'd64('h40) & not 'd8('h8) as I assumed. I am confused by this. If I start writing data in Bank 0, Row 0 & starting from Column 0, with burst lenght 8 & data port width 64, each 64 bit data will be stored in Columns 0 - 7 since each Column can store 64. Then for the next burst I have to give app_addr = 'h8 & not 'h40.

 

The simulation of the example design of MIG writes 64 bit data in Columns 0-7 then Columns 40-47, 80-87 & so on. Why is nothing written in Columns 08-3F?

 

Are my assumptions in the first paragraph wrong?

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Xilinx Employee
Xilinx Employee
16,098 Views
Registered: ‎07-11-2011

Re: MIG DDR3 Memory Addressing confusion for Virtex 6 on ML605 kit

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Hi,

 

1.Your understanding of the addressing concept(row, bank and cloumn) is correct

The link you pointed is started with ML605 but I see UG388 which is actually applicable for Spartan6 and the addressing concepts are a bit different

 

If you are using 64bit DIMM, Burst Length = 8 , UI_Data_Width = 256, then one UI command and 2 UI app data words constitute one memory burst length.

 

Please refer UG406 Chapter -1 -> Interfacing with core ->User Interface -> Memory Address Mapping for Bank-Row-Column Mode in the UI Module and  Memory Address Mapping for Row-Bank-Column Mode in the UI Module tables for more detials

 

 

 

For sequential access you can tie app_addr[2:0] = 000 and increment app_addr[27:3] by one.

For random access as you know the mapping you can assign any coulmn or row value that you like.

 

2. Simulation of example design address will be based on CMD_PATTERN set in sim_tb_top or appropriate top level file.

You can refer UG406 Traffic Generator Parameters for more details

 

Hope this helps

 

-Vanitha

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Xilinx Employee
Xilinx Employee
16,099 Views
Registered: ‎07-11-2011

Re: MIG DDR3 Memory Addressing confusion for Virtex 6 on ML605 kit

Jump to solution

Hi,

 

1.Your understanding of the addressing concept(row, bank and cloumn) is correct

The link you pointed is started with ML605 but I see UG388 which is actually applicable for Spartan6 and the addressing concepts are a bit different

 

If you are using 64bit DIMM, Burst Length = 8 , UI_Data_Width = 256, then one UI command and 2 UI app data words constitute one memory burst length.

 

Please refer UG406 Chapter -1 -> Interfacing with core ->User Interface -> Memory Address Mapping for Bank-Row-Column Mode in the UI Module and  Memory Address Mapping for Row-Bank-Column Mode in the UI Module tables for more detials

 

 

 

For sequential access you can tie app_addr[2:0] = 000 and increment app_addr[27:3] by one.

For random access as you know the mapping you can assign any coulmn or row value that you like.

 

2. Simulation of example design address will be based on CMD_PATTERN set in sim_tb_top or appropriate top level file.

You can refer UG406 Traffic Generator Parameters for more details

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post