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Scholar dgisselq
Scholar
631 Views
Registered: ‎05-21-2015

MIG DDR3 SDRAM controller responding without request

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See the attached .vcd file from a WB to AXI converter (source code also included):

  1. Bridge requests 8-consecutive memory reads (i.e. ARVALID held high for 9 cycles, one with ARREADY low)
  2. MIG returns RVALID for 7 cycles.  (Core holds both RREADY and BREADY always high, which you can see from the attached.)  11us later, MIG returns the eighth and last RVALID.
  3. Core then issues four AWVALID & WVALIDs, gets BVALID response
  4. Core then receives from MIG controller two extraneous RVALIDs--RVALIDs that were not preceeded by prior ARVALIDs and thus not requested!

mig-broken.pngTrace, showing extraneous RVALIDs

For reference, AxLEN is set to 0 for all requests, AxID to 0.  Data width is 128 bits.  Memory size is 512MB.  The part is the Artix-7 on the Nexys Video board.  I'm using Vivado version 2019.1.  Trace is taken at the inputs to the MIG core.  (No other Xilinx cores are used in this design.)

Any suggestions?

Dan

(The forum web-app removed the VCD trace.  Apparently VCD files aren't supported here.  I can e-mail the full trace or post it somewhere at your request.  Substance is shown in .png above, but the details can be confirmed from the trace ...)

EDIT: AxLEN is held to zero, for a burst of length 1, not held to 1.

1 Solution

Accepted Solutions
Scholar dgisselq
Scholar
261 Views
Registered: ‎05-21-2015

Re: MIG DDR3 SDRAM controller responding without request

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Ok, I finally found the "bug".

I told the controller I had an "MT41K128M16XX-15E" chip, when the correct value for my board was "MT41K256M16XX-125".  Since the timing is different between the two chips, the MIG core was not expecting a return from a read request as late as it was coming back.

The good news was that my memory capacity just doubled.

The bad news was that I then started receiving critical warnings: "slew property does not exist for objects of type pin" or some such.  Since I didn't find an answer record for it, I'll share the problem and solution of that here as well.  The 128M controller had one fewer address lines.  My top level block didn't have enough address lines for the controller, despite the controller and the MIG declaring  the line just didn't exist in my top level Verilog file.

Now that I've fixed both, the memory controller is working as expected.  (My design still has issues, but those appear to be my own fault, and things I should be able to fix shortly.)

Thanks to everyone who tried to help,

Dan

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5 Replies
Scholar dgisselq
Scholar
513 Views
Registered: ‎05-21-2015

Re: MIG DDR3 SDRAM controller responding without request

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Here's another example of the same thing.  This time, there's 20.5us of no read activity at all preceeding the unexpected RVALID.  (There might be more, but that's all I have in the trace.)

mig-broken-2.png

Dan

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Scholar dgisselq
Scholar
502 Views
Registered: ‎05-21-2015

Re: MIG DDR3 SDRAM controller responding without request

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Here's another example.  This time the interface is idle--completely (no reads or writes) for 20.5us (2,050 clocks at 100MHz) before the write shown below.  As always, AxLEN=0, WLAST=1, etc.

mig-broken-3.png

Dan

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Scholar dgisselq
Scholar
451 Views
Registered: ‎05-21-2015

Re: MIG DDR3 SDRAM controller responding without request

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If I don't hold RREADY high, the RVALID just sticks ... (which is probably what it should do, still struggling with why RREADY is high without a prior request in the first place).  This rules out RVALID being only generated if RREADY is high.

mig-broken-4.png

Still not sure where to look to debug this in the first place.

Dan

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Scholar dgisselq
Scholar
300 Views
Registered: ‎05-21-2015

Re: MIG DDR3 SDRAM controller responding without request

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Ok, so ... I rebuilt the project from scratch using 2018.3.  Same results.  Along the way, I discovered I was using 2018.3 above and not 2019.1 or if 2019.1 it wasn't clearly 2019.1.

I'm now trying to rebuild under 2019.1 to see if it helps.

I've traced the bug internally to a memory read used to keep the PLLs locked.  The STB signal resulting from this read goes into a hard FIFO.  The FIFO is then read on every clock, and in this case it should've been ignored and was not.

I'm still digging.  Many thanks to the Xilinx team that has been helping (off forum).

Dan

 

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Scholar dgisselq
Scholar
262 Views
Registered: ‎05-21-2015

Re: MIG DDR3 SDRAM controller responding without request

Jump to solution

Ok, I finally found the "bug".

I told the controller I had an "MT41K128M16XX-15E" chip, when the correct value for my board was "MT41K256M16XX-125".  Since the timing is different between the two chips, the MIG core was not expecting a return from a read request as late as it was coming back.

The good news was that my memory capacity just doubled.

The bad news was that I then started receiving critical warnings: "slew property does not exist for objects of type pin" or some such.  Since I didn't find an answer record for it, I'll share the problem and solution of that here as well.  The 128M controller had one fewer address lines.  My top level block didn't have enough address lines for the controller, despite the controller and the MIG declaring  the line just didn't exist in my top level Verilog file.

Now that I've fixed both, the memory controller is working as expected.  (My design still has issues, but those appear to be my own fault, and things I should be able to fix shortly.)

Thanks to everyone who tried to help,

Dan

View solution in original post