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muscat
Observer
Observer
2,563 Views
Registered: ‎09-27-2011

MIG DDR3 questions (about delays and buffers depthes)

Hello, I've read the UG 586, but I didn't fiund answers for my questions

 

1) What is the maximum able delay between sending read-command and appearance  data on app_rd_data?

 

2) What is the depth of input buffers for data? I mean how many packets can you send on app_wsf_data line, without sending any write command?

 

3) Do you use control of delay, between sending data and commands?

I've made my own traffic generator in testbench and all the times data where reading faster, then addresses. But I didn't find in UG something about it, so In my RTL-project, where I'm sending packets,  I have to use control "If current number of sent addresses is smaller or equal number of sent words?". It makes my algorithm more complicated. 

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criley
Xilinx Employee
Xilinx Employee
2,532 Views
Registered: ‎08-16-2007

1) Checkout http://www.xilinx.com/support/answers/45644.htm

2) The command buffers are 8 deep.

3) The write data must be sent within 2 clock cycles before the write command is given but there is no dependency on how long write data needs to be sent after the write command. Not sure if that''s what you were asking...

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