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tmacqui
Observer
Observer
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Registered: ‎02-14-2019

MIG Series 7 DDR3L Reduce Clock rates to lower interface speed operation

Hello,
I am using a DDR3L device (MT41K512M8DA-107) with an Atrix 7 using the MIG DDR generator.
I have LVDS oscillators at SYS_CLK=322.2656MHz and REF_CLK=200MHz. The MIG approves the ball selection.
The MT41K512M8DA has a max clk period which should allow interface operation at very low speeds, say 100MHz.
With these parameters, Can you tell me you tell me how to set the MIG to define a DDR3L interface to run at
100MHz?

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kren
Moderator
Moderator
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Registered: ‎08-21-2007

MIG IP doesn't support the frequency at 100MHz. You can find the minimun frequency supported by MIG IP in the IP wizard.

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tmacqui
Observer
Observer
468 Views
Registered: ‎02-14-2019

Hello,

Yes. I am using the MIG IP generator

I am using a DDR3L device (MT41K512M8DA-107) with an Atrix 7 using the MIG DDR generator.
The SYS_CLK=322.2656MHz and REF_CLK=200MHz. The MIG approves the ball selection.
The MT41K512M8DA DDR3L has a max clk period which should allow interface operation at lower speeds, lower than SYS_CLK rate.  With these parameters, Can you tell me how to set the MIG to define a DDR3L interface to run at a lower rate using the MIG Generator?  Where are the settings to do so?

 

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tmacqui
Observer
Observer
463 Views
Registered: ‎02-14-2019

I have attached the MIG screen.

The SYS_CLK(+/-) LVDS OSC is set to 3202 ns = 312.2656 MHz

Memory type MT41K512M8DA-107

>>> The "PHY to Controller Clock Ratio" is grayed out (it appears to be set to 4:1). <<<

With these settings:

1) What is the operating speed of the DDR3 memeory interface ?

2) I need to make the operting speed lower than SYS_CLK rate. How can I do this using the MIG settings? 

3) Why is the "PHY to Controller Clock Ratio"  grayed out indicating it cannot be modified from the 4:1 setting? 

 

MIG_SSR3_312p2556.png
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