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sheladiya_vijay
Explorer
Explorer
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Registered: ‎12-10-2012

MIG Simulation: ERROR: Activate Failure. Initialization sequence is not complete

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Hi,

 

I'm trying to simulate 7 Series MIG generated using Vivado 2013.4 for XC7K160T device and MT16JTF51264HZ-1G SODIMM module.

 

I tried it by simulating it standalone using Modelsim 10.2c, without Vivado. I also tried it with Vivado. But it gives same error like: "ERROR: Activate  Failure.  Initialization sequence is not complete".

 

Thanks,

Vijay

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vsrunga
Xilinx Employee
Xilinx Employee
16,457 Views
Registered: ‎07-11-2011

So in which case the error occurs?

If this is in your full design and you are using your own test becnh did you check if test bench maps the model correctly as in sim_tb_top?

Are all the top level parameters cross checked and hierarchy of the files is correct?

did you see any phy end FPGA signals toggling in simulation or in underterminate or high impedance state?

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yenigal
Xilinx Employee
Xilinx Employee
9,208 Views
Registered: ‎02-06-2013

Hi

 

Is this issue seen with MIG example design simulation or MIG with your own testbench.

 

Have you generated the MIG simulation model during core generation.

Regards,

Satish

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sheladiya_vijay
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Registered: ‎12-10-2012

Hi Satish,

 

I simulated MIG example design, it goes well without any issue. I tried it with Vivado Simulator and Modelsim as well.

 

Yes, I have generated memory model during core generation.

 

Thanks,

Vijay

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vsrunga
Xilinx Employee
Xilinx Employee
16,458 Views
Registered: ‎07-11-2011

So in which case the error occurs?

If this is in your full design and you are using your own test becnh did you check if test bench maps the model correctly as in sim_tb_top?

Are all the top level parameters cross checked and hierarchy of the files is correct?

did you see any phy end FPGA signals toggling in simulation or in underterminate or high impedance state?

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

sheladiya_vijay
Explorer
Explorer
9,173 Views
Registered: ‎12-10-2012

Hi vsrunga,

 

You are right...I cross checked my design with example design and I found that there was a wrong assignment to ddr3_addr_sdram and ddr3_ba_sdram. I corrected it and it is working fine now.

 

Thanks all...

 

Regards,

Vijay

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